Increased jitter sensitivity in continuous- and discrete-time ΣΔ modulators due to finite OpAmp settling speed

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 2543-2546

  Ortmanns, Maurits ^a   Gerfers, Friedel ^b   Manoli, Yiannos ^c  

^a Sci worx GmbH   (Germany)

^b NXP SEMICONDUCTORS   (Netherlands)

^c UNIVERSITY OF FREIBURG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

A/D CONVERTER; CLOCK-JITTER; DISCRETE-TIME; FINITE GAIN; GAIN BANDWIDTH; LOW-BANDWIDTH; NONIDEAL; SETTLING SPEED; SIGMA-DELTA; SWITCHED CAPACITOR;

CAPACITANCE; CAPACITORS; CLOCKS; CONTINUOUS TIME SYSTEMS; DELTA SIGMA MODULATION; MODULATION; TIMING JITTER;

MODULATORS;

EID: 34547240159     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465144     Document Type: Conference Paper

References (7)

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3. M. Ortmanns, F. Gerfers, and Y. Manoli, "Jitter insensitive feedback DAC for continuous-time ΣΔ modulators," in Proc. IEEE Int. Conf. on Electronics, Circuits and Syst., 2001, pp. 1049-1052.
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