Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability

CODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis

Volumn , Issue , 2006, Pages 100-105

  Ragel, Roshan G ^a   Parameswaran, Sri ^a  

^a UNIVERSITY OF NEW SOUTH WALES   (Australia)

Author keywords

Control flow checking; Embedded processor reliability; Hardware software technique; Micro instruction routines; Preemptive fault detection; Reliable processors

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; CONTROL SYSTEMS; FAULT DETECTION; PROGRAM PROCESSORS; RELIABILITY;

CONTROL FLOW CHECKING; MICRO-INSTRUCTION ROUTINES; PROGRAM FLOW; RELIABLE PROCESSORS;

EMBEDDED SYSTEMS;

EID: 34547163438     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1176254.1176280     Document Type: Conference Paper

References (37)

1. Z. Alkhalifa et al. Design and evaluation of system-level checks for on-line control flow error detection. IEEE Transaction on Parallel and Distributed Systems, pages 627-641, 1999.
2. S. Bagchi et al. Hierarchical error detection in a software implemented fault tolerance (sift) environment. IEEE Transactions on Knowledge and Data Engineering, 12:203-224, March/April 2000.
3. X. Delord and G. Saucier. Control flow checking in pipelined RISC microprocessors: the Motorola MC88100 case study. In EUROMICRO '90, pages 162-169, June 1990.
4. X. Delord and G. Saucier. Formalizing Signature Analysis for Control Flow Checking of Pipelined RISC Microprocessors. In Test conference, pages 936-945, October 1991.
5. B. Eschermann. On combining off-line BIST and on-line control flow checking. In FTCS-22, pages 298-305, July 1992.
6. J. A. Fisher. Customized instruction-sets for embedded processors. In DAC'99, pages 253-257,1999.
7. J. A. Fisher, R Faraboschi, and G. Desoli. Custom-fit processors: letting applications define architectures. In MICRO29, pages 324-335, 1996.
8. J. Gaisler. Concurrent error-detection and modular fault-tolerance in a 32-bit processing core for embedded space flight applications. In FTCS'94, pages 128-130, 1994.
9. O. Goloubeva et al. Soft-error detection using control flow assertions. In DFT'03, pages 581-588, November 2003.
10. O. Goloubeva et al. Improved software-based processor control-flow errors detection technique. In Reliability and maintainability symposium, pages 583-589, January 2005.
11. M. R. Guthaus et al. Mibench: A free, commercially representative Embedded Benchmark Suite. IEEE 4th Annual Workshop on Workload Characterization, pages 83-94, December 2001.
12. G. Kanawati et al. Evaluation of integrated system-level checks for on-line error detection. In Computer performance and dependability symposium, pages 292-301, September 1996.
13. R. Leveugle, T. Michel, and G. Saucier. Design of Microprocessors with Built-in On-line Test. In FTCS-20, pages 450-456, June 1990.
14. D. J. Lu. Watchdog processors and structural integrity checking. IEEE Trans. Computers, 31(7):681-685, 1982.
15. M. R. Lyu, editor. Software Fault Tolerance. John Wiley and Sons Ltd, 1995.
16. H. Madeira and J. Silva. On-line signature learning and checking: experimental evaluation. In COMPEURO'91, pages 642-643, July 1991.
17. A. Mahmood and E. J. McCluskey. Concurrent error detection using watchdog processors - a survey. IEEE Trans. Computers, 37(2): 160-174, 1988.
18. L. McFearin and V. Nair. Control-flow checking using assenions. In DCCA '5, pages 103-112. IEEE Computer Society Press, September 1995.
19. T. Michel, R. Leveugle, and G. Saucier. A new approach to control flow checking without program modification. In FTCS21, pages 334-341, 1991.
20. T. Michel et al. An application specific microprocessor with two-level built-in control flow checking capabilities. In EURO ASIC92, pages 310-313, 1992.
21. G. Miremadi et al. Two software techniques for on-line error detection. In FTCS22, pages 328-335, July 1992.
22. G. Miremadi et al. Use of time and address signatures for control flow checking. In DCCS'5, pages 201-221, September 1995.
23. V. S. S. Nair et al. Design and evaluation of automated high-level checks for signal processing applications. In spie advanced algorithms and architectures for signal processing conference, pages 292-301, August 1996.
24. M. Namjoo. Techniques for concurrent testing of vlsi processor operation. Test Conference, pages 461-468, 1982.
25. J. Ohlsson and M. Rimen. Implicit signature checking. In FTCS'25, pages 218-227, 1995.
26. J. Ohlsson, M. Rimen, and U. Gunneflo. A study of the effects of transient fault injection into a 32-bit rise with built-in watchdog. In FTCS'22, pages 316-325, 1992.
27. J. Peddersen et al. Rapid Embedded Hardware/Software System Generation. In In VLSID'05, pages 111-116, 2005.
28. B. Ramamurthy and S. Upadhyaya. Watchdog processor-assisted fast recovery in distributed systems. In Fifth Dependable computing for critical applications, pages 125-134, 1995.
29. T. Rao. Error coding for arithmetic processors. 1974.
30. N. Saxena and E. McCluskey. Control-flow checking using watchdog assists and extended-precision checksums. IEEE Transactions on Computers, pages 554-558, 1990.
31. M. Schuette and J. Shen. Processor control flow monitoring using signatured instruction streams. IEEE Trans. Computers, pages 264-276, March 1987.
32. M. A. Schuette et al. Experimental evaluation of two concurrent error detection schemes. In FTCS'16, pages 138-143, July 1986.
33. J. Sosnowski. Detection of control flow errors using signature and checking instructions. IEEE International Test Conference, pages 81-88, 1988.
34. The PEAS Team. ASIP Meister, Available at http://www.eda-meister.org/ asip-meister/, 2002.
35. S. Upadhyaya and B. Ramamurthy. Concurrent process monitoring with no reference signatures. IEEE Transactions on Computers, 43:475-480, April 1994.
36. K. Wilken and J. Shen. Continuous signature monitoring: low-cost concurrent detection of processor control errors. Computer-Aided Design of Integrated Circuits and Systems, pages 629-641, June 1990.
37. S. S. Yau and F. Chen. An approach to concurrent control flow checking. IEEE Trans. Software Eng., 6(2):126-137, 1980.