Architectural support for safe software execution on embedded processors

CODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis

Volumn , Issue , 2006, Pages 106-111

  Arora, Divya ^a   Raghunathan, Anand ^b   Ravi, Srivaths ^b   Jha, Niraj K ^a  

^a Princeton University   (United States)

^b NEC LABORATORIES AMERICA   (United States)

Author keywords

Extensible processors; Memory safety; Type safety

Indexed keywords

EMBEDDED PROCESSORS; EXTENSIBLE PROCESSOR; HEAP OVERFLOW; SYSTEM SECURITY;

COMPUTER PROGRAMMING LANGUAGES; PROGRAM PROCESSORS; SECURITY OF DATA; SOFTWARE RELIABILITY; STORAGE ALLOCATION (COMPUTER);

EMBEDDED SYSTEMS;

EID: 34547144265     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1176254.1176281     Document Type: Conference Paper

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