The UltraSPARC T1: A power-efficient high-throughput 32-thread SPARC processor

2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006

Volumn , Issue , 2006, Pages 27-30

  Leon, Ana Sonia ^a,b   Sheahan, Denis ^b  

^a IEEE

^b SUN MICROSYSTEMS   (United States)

Author keywords

Chip MultiThreading (CMT); DSA; EM; GOI; High bandwidth; Law power; Multicore; NBTI; Niagara; OpenSPARC; Power management; Reliability; RSA; SSL; T1000; T2000; Thermal management; Throughput performance; UltraSPARC T1

Indexed keywords

CHIP MULTITHREADING (CMT); POWER MANAGEMENT; THROUGHPUT COMPUTING; THROUGHPUT PERFORMANCE;

BANDWIDTH; CMOS INTEGRATED CIRCUITS; INTERFACES (COMPUTER); JAVA PROGRAMMING LANGUAGE; SERVERS; TEMPERATURE CONTROL; VIDEO STREAMING;

MICROPROCESSOR CHIPS;

EID: 34250882802     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2006.357843     Document Type: Conference Paper

References (11)

1. M. Horowitz and W. Dally, "How scaling will change processor architecture," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech Papers, Feb. 2004, pp. 132-133.
2. W. A. Wulf and S. A. McKee, "Hitting the Memory Wall: Implications of the Obvious," ACM Computer Architecture News, Vol. 23, No. 1, March 1995, p. 20-24
3. Maurice V. Wilkes, "The Memory Gap and the Future of High Performance Memories," ATT Research Laboratories - Cambridge, UK (white paper, 2001)
4. P. Kongetira, "A 32-Way Multithreaded SPARC Processor", presented at 16th Hot Chips Symp., Stanford, CA, Aug., 2004.
5. P. Kongetira, et al., "A 32-Way Multithreaded SPARC Processor," in IEEE Micro, Vol. 25. pp. 21-29, Mar., 2005
6. A. S. Leon, et al., "A Power-Efficient High Throughput 32-Thread SPARC Processor," in IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech Papers, Feb. 2006, pp. 98-99.
7. J. D. Davis, et al., "Maximizing CMT Throughput with Mediocre Cores," In Proceedings of the 14th International Conf. on Parallel Architectures and Compilation Techniques, Sep. 2005, pp. 51-62.
8. See the following website for further information on OpenSPARC Tl: http://www.opensparc.net/
9. A. S. Leon, et al., "The UltraSPARC Tl Processor: CMT Reliability," to be presented at IEEE Custom Integrated Circuits Conference (CICC), Sept., 2006
10. R. Hetherington, "Early Experience with Applications Scaling on Aggressive Chip Muli-Threading: Niagara," in IEEE Vail 2006.
11. SPECjbb2005 Sun Fire T2000 (1 chip, 8 cores) 74, 365 bops, Sun Fire T1000 (1 chip, 8 cores) 60,323 bops; SPECweb2005 Sun Fire T2000 (8 cores, 1 chip) 14001 composite; SPECjAppServer2004 Sun Fire T2000 (8 cores, 1 chip) 615.64 JOPS@Standard; SPECjAppServer2004 7 Sun Fire T2000's (56 cores, 7 chips) & 1 Sun Fire E6900 (40 cores, 20 chips) 4098.77 JOPS@Standard. SPEC, SPECweb, SPECjbb, SPECjAppServer, reg tm of Standard Performance Evaluation Corporation. Results www.spec.org as of 7/20/06.