A 10-GHz CMOS PLL with an agile VCO calibration

2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Volumn , Issue , 2005, Pages 213-216

  Lai, Yu Jen ^a   Lin, Tsung Hsien ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POTENTIAL; PHASE LOCKED LOOPS; SIGNAL ANALYSIS; TUNING; VARIABLE FREQUENCY OSCILLATORS;

FREQUENCY CALIBRATION CIRCUIT; VCO CALIBRATION; VCO TUNING;

CMOS INTEGRATED CIRCUITS;

EID: 34250782111     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2005.251703     Document Type: Conference Paper

References (4)

1. T.-H. Lin and W. J. Kaiser, "A 900-MHz 2.5-mA CMOS Frequency Synthesizer with an Automatic SC Tuning Loop," IEEE J. of Solid-State Circuits, vol. 36, pp. 424-431, Mar. 2001.
2. W. B. Wilson, U.-K. Moon, K. R. Lakshmikumar, and L. Dai, "A CMOS Self-Calibrating Frequency Synthesizer," IEEE J. of Solid-State Circuits, vol. 35, pp. 1437-1444, Oct. 2000.
3. A. Jerng and C. G. Sodini, "The Impact of Device Type ans Sizing on Phase Noise Mechanisms," IEEE JSSC, pp. 360-369, Feb. 2005.
4. K. Shu, E. Sanchez-Sinencio, J. Silva-Martinez, and S. H. K. Embabi, "A 2.4-GHz Monolithic Fractional-N Frequency Synthesizer with Robust Phase-Switching Prescaler and Loop Capacitance Multiplier," IEEE J. of Solid-State Circuits, vol. 38, pp. 866-874, June 2003.