A low-power dual-band WLAN CMOS receiver

2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Volumn , Issue , 2005, Pages 397-400

  Kao, Shiau Wen ^a   Kuo, Ming Ching ^a   Wang, Chao Shiun ^b   Lee, Yi Bin ^a   Chen, Chih Hung ^a   Su, Peng Un ^a   Yang, Tzu Yi ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUITS; BANDWIDTH; CMOS INTEGRATED CIRCUITS; CUTOFF FREQUENCY; LOW PASS FILTERS; NOISE FIGURE; WIRELESS LOCAL AREA NETWORKS (WLAN);

ANALOG BASEBAND CIRCUITRY; MULTISTANDARDS; PROGRAMMABLE GAIN;

SIGNAL RECEIVERS;

EID: 34250697500     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2005.251749     Document Type: Conference Paper

References (8)

1. WWiSE Proposal: High throughput extension to the 802.11 Standard, January, 2005.
2. IEEE P802.11 Wireless LANs - TGn Sync Proposal Technical Specification, May, 2005.
3. M. Zargari, et al., "A single-chip dual-band tri-mode CMOS transceiver for 802.11a/b/g WLAN," ISSCC Dig. Tech. Papers, pp. 96-97, Feb., 2004.
4. L. Perraud, et al., "A Direct-Conversion CMOS Transceiver for the 802.11a/b/g WLAN Standard Utilizing a Cartesian Feedback Transmitter," IEEE J. Solid-State Circuits, Vol. 39, Issue 12, pp. 2226-38, Dec. 2004.
5. R. Magoon, A. Molnar, "RF Local Oscillator Path for OSM Direct Conversion Transceiver with True 50% Duty Cycle Divide by Three and Active Third Harmonic Cancellation," IEEE RFIC Symposium, pp. 23-26, June. 2002.
6. O. Palmisano, "An Optimized Compensation Strategy for Two-Stage CMOS OP AMPS," IEEE Transactions on Circuits and Systems, vol.42 No.3, March 1995.
7. Jarkko Jussila, Analog Baseband Circuits for WCDMA Direct-Conversion Receivers, Doctoral Thesis, Helsinki University of Technology, Espoo, Finland, 2003.
8. A. M. Durham, "Circuit Architectures for High Linearity Monolithic Continuous-Time Filtering," IEEE Transactions on Circuit and Systems- H : Analog and Digital Processing, Vol. 39, NO. 9, September 1992.