A new method for mapping ultra-shallow junction leakage currents

Extended Abstracts of the Sixth International Workshop on Junction Technology, IWJT '06

Volumn , Issue , 2006, Pages 100-103

  Chen, James T C ^a   Dimitrova, Tatiana ^a   Dimitrov, Dimitar ^a  

^a Four Dimensions Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIAS VOLTAGE; CONFORMAL MAPPING; ELECTRIC RESISTANCE; SEMICONDUCTOR JUNCTIONS;

LEAKAGE MEASUREMENT; SHEET RESISTANCE LEAKAGE CURRENT; ULTRA SHALLOW JUNCTION;

LEAKAGE CURRENTS;

EID: 34250219969     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iwjt.2006.220870     Document Type: Conference Paper

References (5)

1. J.T.C.Chen and W. Liu, USJ-2005. (Daytona Beach, Florida, USA, 2005) p. 103.
2. V.N.Faifer, et al., MRS-Spring 2004, Symp.C, 810 (2004) 475.
3. S.M. Sze, Physics of Semiconductor Devices, (Second Edition, Wiley, NY, 1981), p. 91, 537.
4. J. Borland et al., to be published in SST, May, 2006.
5. O.K. Schroder, Semiconductor Material and Device Characterization, (Third Edition, IEEE Press, Wiley-Interscience, NY, 2006), p. 604.