A CMOS circuit for STDP with a symmetric time window

International Congress Series

Volumn 1301, Issue , 2007, Pages 152-155

  Tanaka, Hideki ^a   Morie, Takashi ^a   Aihara, Kazuyuki ^b  

^a KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

^b INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

LSI implementation; Neural network; Spiking neuron; STDP

Indexed keywords

EID: 34250184468     PISSN: 05315131     EISSN: None     Source Type: Book Series    
DOI: 10.1016/j.ics.2006.12.029     Document Type: Article

References (5)

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3. Tovar G.M., et al. Precisely-timed synchronization among spiking neural circuits on analog VLSIs", 2006 RISP Int. Nonlinear Circuits and Signal Processing (NCSP2006) (2006) 62-65
4. Sasaki K., Morie T., and Iwata A. A Spiking Neural Network with Negative Thresholding and its Applications to Associative Memory. IEEE Int. Midwest Symp. on Circuits and Systems (MWSCAS2004) vol. 3 (2004) 89-92
5. Tanaka H., Morie T., and Aihara K. An analog CMOS circuit for spiking neuron models. Brain-Inspired IT II, International Congress Series (2006), Elsevier 217-220