An analog CMOS circuit for spiking neuron models

International Congress Series

Volumn 1291, Issue , 2006, Pages 217-220

  Tanaka, Hideki ^a   Morie, Takashi ^a   Aihara, Kazuyuki ^b  

^a KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

^b INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

LSI implementation; Neural network; Spiking neuron

Indexed keywords

EID: 33744939980     PISSN: 05315131     EISSN: None     Source Type: Book Series    
DOI: 10.1016/j.ics.2006.02.036     Document Type: Article

References (4)

1. Maass W. Networks of spiking neurons: the third generation of neural network models. Neural Networks 10 9 (1997) 1659-1671
2. Maass W., and Bishop M.C. Pulsed Neural Networks (1999), MIT Press, Cambridge, MA
3. Sasaki K., Morie T., and Iwata A. A spiking neural network with negative thresholding and its applications to associative memory. IEEE Int. Midwest Symp. on Circuits and Systems (MWSCAS2004) vol. 3 (2004) 89-92
4. Tanaka H., Morie T., and Aihara K. Associative memory operation in a Hopfield-type spiking neural network with modulation of resting membrane potential. International Symp. on Nonlinear Theory and its Applications (NOLTA) (2005) 313-316