Partitioning scheme in lateral asymmetric MOST

ESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference

Volumn 2006-January, Issue , 2006, Pages 307-310

  Roy, A S ^a   Chauhan, Y S ^a   Sallese, J M ^a   Enz, C C ^a,b   Ionescu, A M ^a   Declercq, M ^a  

^a EPFL   (Switzerland)

^b CSEM   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

MOSFET DEVICES;

CAPACITANCE PROPERTIES; DEVICE SIMULATIONS; DOPING VARIATION; HIGH-VOLTAGE MOSFET; LATERAL ASYMMETRIC MOSFET; UNUSUAL BEHAVIORS;

CAPACITANCE;

EID: 34249901836     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/essder.2006.307699     Document Type: Conference Paper

References (5)

1. A.C.T. Aarts et al."New fundamental insights into capacitance modeling of laterally nonuniform MOS devices", IEEE Trans. Electron Devices, pp 270, 2006
2. A.C.T. Aarts et al."Capacitance modeling of laterally non-uniform MOS devices", IEDM Tech. Dig., pp 751, 2004
3. S.-Y. OH et al."Transient analysis of MOS transistors",IEEE Trans. Electron Devices, pp 1571, 1980
4. C. J. Ranuárez et al."Modeling the Partition of Noise From the Gate-Tunneling Current in MOSFETs",IEEE Electron Dev. Let, pp 550, 2005
5. J.-M. Sallese et al. "Inversion charge lineariazation in MOSFET modeling and rigorous derivation of the EKV compact model", Solid-State Electronics,pp 677, 2003.