A reliable clock tree design methodology for ASIC designs

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2000-January, Issue , 2000, Pages 269-274

  Chi, Mely Chen ^a   Huang, Shih Hsu ^b  

^a CHUNG YUAN CHRISTIAN UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE SYSTEMS; CLOCK DISTRIBUTION NETWORKS; CMOS INTEGRATED CIRCUITS; DESIGN; ELECTRIC CLOCKS; FORESTRY; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUITS; RESEARCH LABORATORIES; SYNTHESIS (CHEMICAL); TELECOMMUNICATION NETWORKS; TREES (MATHEMATICS);

CLOCK SOURCE; CLOCK TREE SYNTHESIS; CMOS TECHNOLOGY; COMMUNICATIONS RESEARCH LABORATORIES; DEEP SUB-MICRON; DESIGN METHODOLOGY; RELIABLE METHODS; SINGLE CLOCK;

CLOCKS;

EID: 34248568113     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2000.838882     Document Type: Conference Paper

References (7)

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3. A. Takahashi and Y. Kajitani, "Performance and Reliability Driven Clock Scheduling of Sequential Logic Circuits", in Proc. of ASP-DAC, pp. 37-42, 1997.
4. C. Y. Lee, Y. R. Lin, M. C. Chi, S. H. Huang, K. C. Jung, "Clock Tree Synthesis Flow", in Technical Journal of Computer & Communications Research Laboratories, pp. 28-31, 1997.
5. S. H. Huang", A Design Methodology for a 0.35um IC Project", in Technical Journal of Computer & Communications Research Laboratories, pp. 42-47, 1999.
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7. Apollo User Guide 1998.4, Avant! Inc.