Enhancing CMOS transistor performance using lattice-mismatched materials in source/drain regions

Third International SiGe Technology and Device Meeting, ISTDM 2006 - Conference Digest

Volumn 2006, Issue , 2006, Pages

  Yeo, Yee Chia ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 34247468014     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. S. Ito et al., IEDM (2000), p. 247.
2. T. Ghani et al., IEDM (2003), p. 978.
3. Y.-C. Yeo et al., MRS Symp., vol. 809, p. 219, (2004);
4. Appl. Phys. Lett. 83, 023103 (2005).
5. K.-J. Chui et al., IEDM (2005), p. 499.
6. [51 K. J. Kuhn et al., IEEE International Semiconductor Manu. Symp. (2001), p. 187.
7. C.-H. Chen et al., Symp. VLSI Technol. (2004), p. 56.
8. Q. Ouyang et al., Symp. VLSI Technol. (2005), p. 28.
9. K.-W. Ang et al., IEDM (2004), p. 1069.
10. K.-W. Ang et al., IEDM (2005), p. 503.