Fast-frequency offset cancellation loop using low-IF receiver and fractional-N PLL

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 54, Issue 3, 2007, Pages 272-276

  Shin, Sangho ^a   Kim, Kyungmin ^a   Lee, Kwyro ^a,b   Kang, Sung Mo ^c  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b LG Electronics Inc   (South Korea)

^c University of California Santa Cruz   (United States)

Author keywords

Frequency offset; frequency synthesizer; low intermediate frequency; stability time to digital converter (TDC)

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; DESIGN; DETECTOR CIRCUITS; FREQUENCY DOMAIN ANALYSIS; PHASE LOCKED LOOPS; SIGNAL RECEIVERS; STABILITY;

FREQUENCY OFFSET; LOW INTERMEDIATE FREQUENCY; OFFSET CANCELLATION LOOP; TIME-TO-DIGITAL CONVERTER;

FREQUENCY SYNTHESIZERS;

EID: 34147133411     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2006.888733     Document Type: Article

References (5)

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