On-board fault-tolerant SAR processor for spaceborne imaging radar systems

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 420-423

  Fang, Wai Chi ^a   Le, Charles ^a   Taft, Stephanie ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN METHODOLOGY; FAULT-TOLERANT; FUNCTIONAL VERIFICATION; HARDWARE ARCHITECTURE; HARDWARE DESIGN; INTEGRATED DESIGNS; LEVEL ALGORITHMS; PERFORMANCE VALIDATION; SAR PROCESSORS; SPACE-BORNE; SYNTHETIC APERTURE RADAR IMAGES; SYSTEM ARCHITECTURES;

IMAGING SYSTEMS; OPTOELECTRONIC DEVICES; RADAR IMAGING; RADAR SYSTEMS; REAL TIME SYSTEMS; SPACE APPLICATIONS; SYNTHETIC APERTURE RADAR; SYNTHETIC APERTURES;

ARCHITECTURAL DESIGN;

EID: 34047255049     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464614     Document Type: Conference Paper

References (4)

1. P. Rosen and M. Davis, "A joint space-borne radar technology demonstration mission for NASA and the Air Force," Proc. IEEE 2003 Aerospace Conf., Big Sky MT, vol. 1, pp. 437-444, March 2003.
2. rd ed., vol. 47, no. 1, pp. 125-128, January 1998.
3. J.C. Curlander and R.N. McDonough, Synthetic Aperture Radar System and Signal Processing, Wiley Interscience, NY, 1991
4. "FPGA Design with Cadence SPW", Datasheet, Cadence Design Systems, Inc, 2002.