A dependable high performance wafer scale architecture for embedded signal processing

IEEE Transactions on Computers

Volumn 47, Issue 1, 1998, Pages 125-128

  Linderman, Richard W ^a,b   Kohler, Ralph L R ^a,b   Linderman, Mark H ^a,b  

^a AIR FORCE RESEARCH LABORATORY   (United States)

^b IEEE   (United States)

Author keywords

Computer reliability; Embedded processing; High speed integrated circuits; Memory hierarchies; Parallel architectures; Wafer scale integration

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; ELECTRONICS PACKAGING; MICROPROCESSOR CHIPS; MULTICHIP MODULES; RANDOM ACCESS STORAGE; RELIABILITY; SIGNAL PROCESSING; WSI CIRCUITS;

EMBEDDED SIGNAL PROCESSING; MEMORY HIERARCHIES; WAFER SCALE SIGNAL PROCESSORS;

PARALLEL PROCESSING SYSTEMS;

EID: 0031647075     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.656096     Document Type: Article

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