High-G drop impact response and failure analysis of a chip packaged printed circuit board

International Journal of Impact Engineering

Volumn 34, Issue 10, 2007, Pages 1655-1667

  Jenq, S T ^a   Sheu, H S ^a   Yeh, Chang Lin ^b   Lai, Yi Shao ^b   Wu, Jenq Dah ^b  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^b ADVANCED SEMICONDUCTOR ENGINEERING INC   (Taiwan)

Author keywords

Drop impact; FEM analysis; High G impact response; Impact failure damage; Solder joints

Indexed keywords

DETECTORS; ELECTRONICS PACKAGING; FAILURE ANALYSIS; NUMERICAL METHODS; PRINTED CIRCUIT BOARDS; SOLDERED JOINTS;

DROP IMPACT; HIGH-G IMPACT RESPONSE; IMPACT FAILURE;

IMPACT TESTING;

EID: 34047156503     PISSN: 0734743X     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.ijimpeng.2006.07.004     Document Type: Article

References (16)

1. Wong EH, Rajoo R, Mai YW, Seah SKW, Tsai KT, Yap LM. Drop impact: fundamentals and impact characterisation of solder joints. In: Proceedings of the 55th electronic components and technology conference, Lake Buena Vista, FL, 2005, p. 1202-9.
2. Irving S, Liu Y. Free drop test simulation for portable IC package by implicit transient dynamics FEM. In: Proceedings of the 54th electronic components and technology conference, Las Vegas, NV, 2004, p. 1062-66.
3. Lall P, Panchagade D, Liu Y, Johnson W, Suhling J. Models for reliability prediction of fine-pitch BGAs and CSPs in shock and drop-impact. In: Proceedings of the 54th electronic components and technology conference, Las Vegas, NV, 2004, p. 1296-1303.
4. Yeh C-L, Lai Y-S. Effect of solder joint shapes on free drop reliability of chip-scale packages. In: Proceedings of the IMAPS Taiwan technical symposium 2004, Kaohsiung, Taiwan, 2004.
5. Wong EH, Lim KM, Lee N, Seah S, Hoe C, Wang J. Drop impact test-mechanics & physics of failure. In: Proceedings of the fourth electronics packaging technology conference, Singapore, 2002, p. 327-33.
6. Luan J-E, Tee TY, Pek E, Lim CT, Zhong Z. Modal analysis and dynamic responses of board level drop test. In: Proceedings of the 5th electronics packaging technology conference, Singapore, 2003, p. 233-43.
7. Tee T.Y., Ng H.S., Lim C.T., Pek E., and Zhong Z. Impact life prediction modeling of TFBGA packages under Board Level Drop Test. Microelectronics Reliability 44 7 (2004) 1131-1142
8. Sheu HS, Jenq ST, Wu J-D, Yeh C-L, Constructing a High G impact environment for testing the advanced electronic packaged circuit board structure. In: Proceedings of the 2004 AASRC/CCAS joint conference, Taichung, Taiwan, 2004.
9. Luan J-E, Tee TY, Novel board level drop test simulation using implicit transient analysis with input-G method. In: Proceedings of the sixth electronics packaging technology conference, Singapore, 2004, p. 671-77.
10. Yeh C.-L., and Lai Y.-S. Support Excitation Scheme for Transient Analysis of JEDEC Board-level Drop Test. Microelectronics Reliability 46 2-4 (2006) 626-636
11. Lai Y.-S., Yang P.-F., and Yeh C.-L. Experimental studies of board-level reliability of chip-scale packages subjected to JEDEC drop test condition. Microelectronics Reliability 46 2-4 (2006) 645-650
12. Yeh C-L, Lai Y-S, Kao C-L. Evaluation of board-level reliability of electronic packages under consecutive drops, microelectronics reliability, in press.
13. JEDEC Solid State Technology Association, JESD22-B110: Subassembly Mechanical Shock, 2001.
14. JEDEC Solid State Technology Association, JESD22-B111: Board level drop test method of component for handheld electronics products, 2003.
15. Sheu HS. Analysis of printed circuit board subjected to low velocity drop impact loading, M.S. thesis, Institute of Aeronautics & Astronautics, National Cheng Kung University, Tainan, Taiwan, 2004.
16. Siewert T, Liu S, Smith DR, Madenim JC. Database for solder properties with emphasis on new lead-free solders, properties of lead-free solders, Release 4.0, NIST & Colorado School of Mines, CO, 2002.