An 830mW, 586kbps 1024-bit RSA chip design

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 2, Issue , 2006, Pages

  Yeh, Chingwei ^a   Hsu, En Feng ^a   Cheng, Kai Wen ^a   Wang, Jinn Shyan ^a   Chang, Nai Jen ^a  

^a Nat'l Chung Cheng University   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL CAPABILITY; POWER OPTIMIZED DESIGNS; SPLIT MODULAR MULTIPLICATION ALGORITHMS; STORAGE ELEMENTS;

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; COMPUTER HARDWARE; COMPUTER SIMULATION; MICROPROCESSOR CHIPS;

LOGIC DESIGN;

EID: 34047134550     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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