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Volumn 1, Issue , 2006, Pages

Design with race-free hardware semantics

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; HAZARDS AND RACE CONDITIONS; SYSTEMS ANALYSIS;

EID: 34047118169     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.243956     Document Type: Conference Paper
Times cited : (4)

References (17)
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    • OSCI, "Non-deterrninism in SystemC", Ch. 5.6 in "Functional Specification for SystemC 2.0", v. 2.0-Q, [Online]. Available: http://www.systemc.org
  • 4
    • 29244476246 scopus 로고    scopus 로고
    • SHIM: A Deterministic Model for Heterogeneous Embedded Systems
    • S. Edwards, O. Tardieu, "SHIM: A Deterministic Model for Heterogeneous Embedded Systems," IEEE Proc. EMSOFT 2005.
    • (2005) IEEE Proc. EMSOFT
    • Edwards, S.1    Tardieu, O.2
  • 5
    • 15044358802 scopus 로고    scopus 로고
    • Hardware/software interface codesign for embedded systems
    • Feb
    • A. Jerraya, W. Wolf, "Hardware/software interface codesign for embedded systems," IEEE Computer, 38(2):63-69, Feb 2005.
    • (2005) IEEE Computer , vol.38 , Issue.2 , pp. 63-69
    • Jerraya, A.1    Wolf, W.2
  • 6
    • 0001383866 scopus 로고
    • An Introduction to Input/Output automata
    • September
    • N. Lynch, E. Tuttle, "An Introduction to Input/Output automata," CWI-Quarterly, 2(3):219-246, September 1989.
    • (1989) CWI-Quarterly , vol.2 , Issue.3 , pp. 219-246
    • Lynch, N.1    Tuttle, E.2
  • 7
    • 0000087207 scopus 로고
    • The semantics of a simple language for parallel programming
    • G. Kahn, "The semantics of a simple language for parallel programming," Information Processing 74, 1974.
    • (1974) Information Processing , vol.74
    • Kahn, G.1
  • 9
    • 34047151038 scopus 로고    scopus 로고
    • The Kahn principle for networks of synchronous endochronous
    • D. Potop, "The Kahn principle for networks of synchronous endochronous," Proc. of FMGALS 2003.
    • (2003) Proc. of FMGALS
    • Potop, D.1
  • 12
    • 33645692468 scopus 로고    scopus 로고
    • AES-Based Cryptographic and Biometrie Security Coprocessor IC in 0.18-um CMOS Resistant to Side-Channel Power Analysis Attacks
    • Kyoto
    • D. Hwang, K. Tiri, A. Hodjat, B. Lai, S. Yang, P. Schaumont, I. Verbauwhede, "AES-Based Cryptographic and Biometrie Security Coprocessor IC in 0.18-um CMOS Resistant to Side-Channel Power Analysis Attacks," 2005 Symposium on VLSI Circuits, Kyoto.
    • (2005) Symposium on VLSI Circuits
    • Hwang, D.1    Tiri, K.2    Hodjat, A.3    Lai, B.4    Yang, S.5    Schaumont, P.6    Verbauwhede, I.7
  • 14
    • 79957547537 scopus 로고    scopus 로고
    • Verilog Nonblocking Assignments With Delays, Myths & Mysteries
    • Boston
    • C. Cummings, "Verilog Nonblocking Assignments With Delays, Myths & Mysteries," Synopsys User Group Meeting (SNUG), Boston, 2002.
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  • 16
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  • 17
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    • SystemVerilog 2-State Simulation Performance and Verification Advantages
    • Boston
    • C. Cummings, L. Bening, "SystemVerilog 2-State Simulation Performance and Verification Advantages", Synopsus User Group Meeting (SNUG), Boston, 2004.
    • (2004) Synopsus User Group Meeting (SNUG)
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.