Smart bit-width allocation for low power optimization in a systemC based ASIC design environment

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Mallik, Arindam ^a   Sinha, Debjit ^a   Banerjee, Prith ^b   Zhou, Hai ^a  

^a Northwestern University   (United States)

^b 1120 Science and Engineering Offices   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; EMBEDDED SYSTEMS; HEURISTIC METHODS; OPTIMIZATION; SYSTEMS ANALYSIS;

POWER OPTIMIZATION; QUANTIZATION ERROR;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 34047117424     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.243996     Document Type: Conference Paper

References (12)

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