Designing MRF based error correcting circuits for memory elements

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Nepal, K ^a   Bahar, R I ^a   Mundy, J ^a   Patterson, W R ^a   Zaslavsky, A ^a  

^a BROWN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CODES (STANDARDS); MARKOV PROCESSES; STORAGE ALLOCATION (COMPUTER);

ERROR CORRECTING CODES (ECC); MARKOV RANDOM FIELDS (MRF); MEMORY MEMORY;

ERROR CORRECTION;

EID: 34047107324     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.244144     Document Type: Conference Paper

References (7)

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4. R. I. Bahar, J. Mundy, and J. Chen. A probabilistic-based design methodology for nanoscale computation. In ICCAD, Nov. 2003.
5. K. Nepal, R. I. Bahar, J. Mundy, W. R. Patterson, and A. Zaslavsky. Designing logic circuits for probabilistic computation in the presence of noise. In DAC, June 2005.
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7. http://www-device.eecs.berkeley.edu/~ptm/.