A dynamically reconfigurable packet-switched network-on-chip

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Pionteck, Thilo ^a   Albrecht, Carsten ^a   Koch, Roman ^a  

^a UNIVERSITY OF LÜBECK   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); ROUTING ALGORITHMS; SCALABILITY;

DYNAMIC ROUTING TABLES; INTERCONNECTION SCHEMES; RECONFIGURABLILITY;

PACKET NETWORKS;

EID: 34047100461     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.244035     Document Type: Conference Paper

References (2)

1. C. Albrecht, R. Koch, and T. Pionteck. On the design of a loosely-coupled run-time reconfigurable network coprocessor. Workshop on Media and Streaming Processors, Nov. 2005.
2. C. Bobda, A. Ahmadinia, M. Majer, J. Teich, S. Fekete, and J. van der Veen. DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices. In FPL 2005, Tampere, Finland, Aug. 2005.