The 65-nm 16-MB shared on-die L3 cache for the Dual-Core Intel Xeon Processor 7100 Series

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 4, 2007, Pages 846-852

  Chang, Jonathan ^a,b   Huang, Ming ^b   Shoemaker, Jonathan ^b   Benoit, John ^a,b   Chen, Szu Liang ^b   Chen, Wei ^b   Chiu, Siufu ^b   Ganesan, Raghuraman ^b   Leong, Gloria ^b   Lukka, Venkata ^b   Rusu, Stefan ^a,b   Srivastava, Durgesh ^b  

^a IEEE   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Circuit design; Computer architecture; Manufacturability; Microprocessor; On die cache; Power reduction; Reliability; Test

Indexed keywords

DUAL-CORE INTEL XEON PROCESSOR; ON-DIE CACHE; POWER REDUCTION;

BUFFER CIRCUITS; BUFFER STORAGE; LEAKAGE CURRENTS; OPTIMIZATION; STATIC RANDOM ACCESS STORAGE; TRANSISTORS;

PROGRAM PROCESSORS;

EID: 33947644880     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.892185     Document Type: Article

References (6)

1. S. Rusu et al., "A dual core multi threaded Xeon processor with 16MB L3 cache," in IEEE ISSCC 2006 Dig. Tech. Papers, pp. 315-324.
2. J. Chang et al., "The 65-nm 16-MB on-die L3 cache for a dual core multi-threaded Xeon processor," in Symp. VLSI Circuits 2006 Dig. Tech. Papers, pp. 158-159.
3. K. Zhang et al., "A SRAM design on 65-nm CMOS technology with integrated leakage reduction scheme," in Symp. VLSI Circuits 2006 Dig. Tech. Papers, pp. 294-295.
4. J. Wuu et al., "The asynchronous 24-MB on-chip level-3 cache for a dual-core Itanium® family processor," in IEEE ISSCC 2005 Dig. Tech. Papers, pp. 488-489.
5. K. Nii et al., "A 90-nm low power 32 K-byte embedded sram with gate leakage suppression circuit for mobile applications," in Symp. VLSI Circuits 2003 Dig. Tech. Papers, pp. 247-250.
6. A. J. Bhavnagarwala et al., " A pico-joule class, 1 GHz, 32 KByte × 64 b DSP SRAM with self reverse bias," in Symp. VLSI Circuits 2003 Dig. Tech. Papers, pp. 251-252.