The future of semiconductor manufacturing

IEEE Robotics and Automation Magazine

Volumn 13, Issue 4, 2006, Pages 16-24

  Pillai, Devadas ^a  

^a INTEL CORPORATION   (United States)

Author keywords

AMHS; Carrier architecture; Cybersecurity; Data architecture; Factory automation; Factory integration; High mix production systems; Material handling systems; Reticle handling; Setups; Ssmall lot; Systems integration; Wafer fabrication

Indexed keywords

COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; FACTORY AUTOMATION; MATERIALS HANDLING; NETWORK PROTOCOLS; NETWORK SECURITY; SECURITY OF DATA; SEMICONDUCTOR DEVICE MANUFACTURE;

CARRIER ARCHITECTURE; CYBERSECURITY; DATA ARCHITECTURE; FACTORY INTEGRATION; FLEXIBLE INFORMATION SYSTEMS ARCHITECTURE; HIGH-MIX PRODUCTION SYSTEMS; RETICLE HANDLING; SETUPS; SYSTEMS INTEGRATION; WAFER FABRICATION;

COMPUTER AIDED MANUFACTURING; SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 33947393559     PISSN: 10709932     EISSN: None     Source Type: Journal    
DOI: 10.1109/MRA.2006.250560     Document Type: Article

References (9)

1. "International technology roadmap for semiconductors (ITRS),*: Semi-conductor Industry Assoc., Dec. 2005.
2. M. Honma and S. Kobayashi, "Next generation 300 mm factory,*: presented at SEMI Sponsored Manufacturing Technology Forum (MTF), Tokyo, Jan. 26, 2006.
3. M. Liu, "High mix manufacturing requirements," presented at International Sematech Manufacturing Initiative (IMSI), Austin, TX, Oct. 2005, keynote speech.
4. J. Pettinato, D. Pillai, "Technology decisions to minimize 450-mm wafer size transition risk," IEEE Trans. Semiconduct. Manufact., vol. 18, no. 4, pp. 501-509, Nov. 2005.
5. B. Subramaniam, C. Golla, D. Pillai, C. Lockwood, "300 mm equipment buffering strategy to maximize fab productivity," in Proc. IEEE Int. Symp. Semiconductor Manufacturing Conf. (ISSM) Technical Poster Session, San Jose, CA, Oct. 2, 2003, pp. 329-332.
6. D. Pillai, B. Edward, J. Dempsey, E. Yellig, "300 mm full factory dynamic simulations for 90 nm and 65 nm IC manufacturing," IEEE Trans. Semicond. Manufact., vol. 17, no. 3, pp. 292-298, June 2004.
7. B. Sohn, D. Pillai, and N. Acker, "300 mm factory design for operational effectiveness," presented at the IEEE/ASMC Conference, SEMICON Europa, Munich, Apr. 2000.
8. P. Silverman, "Moore's law semiconductor economics and wafer size," in ConFab 2006, Las Vegas, NV, May 2006.
9. D. Hutcheson, "Chip insider - Trecenti technologies," VLSI Besearch Inc., Rep., Apr. 3, 2003.