Balanced instruction cache: Reducing conflict misses of direct-mapped caches through balanced subarray accesses

IEEE Computer Architecture Letters

Volumn 5, Issue 1, 2006, Pages 2-5

  Zhang, Chuanjun ^a  

^a AGC Paul S Roel Chair in Construction Engineering and Management   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BALANCED CACHE; BALANCED SUBARRAY ACCESSES; CACHE SUBARRAYS; GRANULARITY;

ASSOCIATIVE STORAGE; CONFORMAL MAPPING; PROGRAMMABLE LOGIC CONTROLLERS; STORAGE ALLOCATION (COMPUTER);

BUFFER STORAGE;

EID: 33947317738     PISSN: 15566056     EISSN: None     Source Type: Journal    
DOI: 10.1109/L-CA.2006.5     Document Type: Article

References (11)

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