Design space exploration for arbitrary FPGA architectures

ICESS 2005 - Second International Conference on Embedded Software and Systems

Volumn 2005, Issue , 2005, Pages 269-275

  Lee, Chee Sing ^a   Ha, Yajun ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GRAPHICAL USER INTERFACES; RESOURCE ALLOCATION; ROUTERS; USER INTERFACES;

ROUTING ARCHITECTURES; ROUTING RESOURCE GRAPHS (RRG); SPACE EXPLORATION;

SPACE RESEARCH;

EID: 33847717150     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICESS.2005.46     Document Type: Conference Paper

References (13)

1. V. Betz. Architecture and CAD for speed and Area Optimization of FPGAs. PhD thesis, University of Thoronto, 1998.
2. V. Setz and J. Rose. Vpr: A new packing, placement and routing tool for fpga research. In Field Programmable Logic and Applications, pages 213-222, 1997.
3. V. Betz and J. Rose. Automatic generation of fpga routing architectures from high-level descriptions. In Field Programmable Gate Arrays, pages 175-184, Monterey, CA, February 2000.
4. S. A. H. C. Ebeling, L. McMurchie and S. Burns. Placement and routing tools for the triptych fpga. IEEE Trans. on VLSI, pages 473-482, December 1995.
5. C. Cheng. Risa: Accurate and efficient placement routability modeling. In ICCAD, pages 690-695, 1994.
6. D. C. Cronquist and L. McMurchie. Emerald: An architecture-driven tool compiler for FPGAs. In Field Programmable Gate Arrays, pages 144-150, 1996.
7. V. George. Low Energy Field-Programmable Gate Array. PhD thesis, University of California, Berkeley, 2000.
8. V. B. J. Swartz and J. Rose. A fast routability-driven router for fpgas. pages 140-149, Monterey, CA, February 1998.
9. S. B. M. Khellah and Z. Vranesic. Minimizing interconnection delays in array-based FPGAs. In CICC, pages 181-184, 1994.
10. J. Rose and S. Brown. Flexibility of interconnection structures for field-programmable gate arrays. Journal of Solid-State Circuits, 26(3):277-282, March 1991.
11. J. R. S. Brown, R. Francis and Z. Vranesic. Field-Programmable Gate Arrays. Kluwer Academic Publishers, Boston, May 1992.
12. K. Shahookar and P. Mazumder. Vlsi cell placement techniques. ACM Computing Surveys, 23(2): 143-220, June 1991.
13. J. R. V. Betz and A. Marquardt. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publisher, 1999.