High performance multi-gate pMOSFETs using uniaxially-strained SGOI channels

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2005, Issue , 2005, Pages 709-712

  Irisawa, Toshifumi ^a   Numata, Toshinori ^a   Tezuka, Tsutomu ^a   Usuda, Koji ^a   Nakaharai, Shu ^a   Hirashita, Norio ^a   Sugiyama, Naoharu ^a   Toyoda, Eiji ^a   Takagi, Shin Ichi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL ESTIMATION; CMOS INTEGRATED CIRCUITS; HIGH ELECTRON MOBILITY TRANSISTORS; SILICON ON INSULATOR TECHNOLOGY; STRAIN RELAXATION;

LATERAL STRAIN RELAXATION; PERFORMANCE ENHANCEMENT; SGOI CHANNELS; UNIAXIALLY-STRAINED;

MOSFET DEVICES;

EID: 33847712554     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. T. Mizuno et al., IEDM Tech. Dig., 809 (2003).
2. C. S. Smith et al., Phys. Rev. B, 94 42 (1954).
3. H. Irie et al., IEDM Tech. Dig., 225 (2004).
4. T. Irisawa et al., VLSI Symp., 178 (2005).
5. K. Rim et al., IEDM Tech. Dig., 351 (2003).
6. T. Tezuka et al., 26 243 EDL (2005).
7. T. Tezuka et al., IEDM Tech. Dig., 946 (2001).
8. S. Nakaharai et al., proc. ICSI3, p129, (2003).
9. K. Usuda et al., Appl. Surf. Sci., Vol.224, 113 (2004).
10. K. Jakub et. al., IEDM Tech. Dig., 437 (2001).
11. K. Jakub et al., IEDM Tech. Dig., 247 (2002).
12. Y. -K Choi., IEDM Tech. Dig., 421 (2001).