90 nm generation, 300 mm wafer low k ILD/Cu interconnect technology

Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003

Volumn , Issue , 2003, Pages 15-17

  Jan, C H ^a   Bielefeld, J ^a   Buehler, M ^a   Chikamane, V ^a   Fischer, K ^a   Hepburn, T ^a   Jain, A ^a   Jeong, J ^a   Kielty, T ^a   Kook, S ^a   Marieb, T ^a   Miner, B ^a   Nguyen, P ^a   Schmitz, A ^a   Nashner, M ^a   Scherban, T ^a   Schroeder, B ^a   Wang, P H ^a   Wu, R ^a   Xu, J ^a   Zawadzki, K ^a   Thompson, S ^a   Bohr, M ^a   more..

^a INTEL CORPORATION   (United States)

Author keywords

Assembly; Atomic layer deposition; Capacitance; Clamps; Compressive stress; Dielectric constant; Dielectric materials; Packaging; Plasma materials processing; Thermal stresses

Indexed keywords

ASSEMBLY; ATOMIC LAYER DEPOSITION; CAPACITANCE; CARBON; CLAMPING DEVICES; COMPRESSIVE STRESS; DIELECTRIC MATERIALS; PACKAGING; PACKAGING MATERIALS; PERMITTIVITY; THERMAL STRESS;

300 MM WAFERS; CARBON DOPED OXIDES; CU METALLIZATION; INTERCONNECT TECHNOLOGY; INTRA-LAYER; PLASMA MATERIALS-PROCESSING;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 33847693798     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2003.1219699     Document Type: Conference Paper

References (3)

1. S. Yang et al., IEDM Tech Dig., 1998, pp 197-200.
2. S. Tyagi et al., IEDM Tech Dig., 2000, pp 561-571.
3. S. Thompson et al., IEDM Tech Dig., 2002, pp 61-64