Design of low power buffer using driver-array for on-chip IPs interconnection

IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings

Volumn 2, Issue , 2003, Pages 1218-1221

  Qiao, Fei ^a   Yang, Huazhong ^a   Wang, Hui ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

Driver array; Interconnection buffer; Low power; Multi stage buffer

Indexed keywords

DESIGN; ELECTRIC POWER SYSTEM INTERCONNECTION;

DESIGN FLOWS; FAN OUT; LOGIC SIGNALS; LOW POWER; MULTI-STAGE BUFFER; NOVEL DESIGN; ON CHIPS;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 33847353046     PISSN: 1523553X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASIC.2003.1277433     Document Type: Conference Paper

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