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Volumn 1, Issue , 2003, Pages 564-567

A study on analog IP blocks for mixed-signal SoC

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SOFTWARE REUSABILITY; SYSTEM-ON-CHIP;

EID: 33847255508     PISSN: 1523553X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASIC.2003.1277612     Document Type: Conference Paper
Times cited : (7)

References (7)
  • 2
    • 0025383839 scopus 로고
    • Opasyn: A compiler for MOS operational amplifiers
    • February
    • Koh, H.Y., Sequin, C. H. and Gray, P. R., "OPASYN: A Compiler for MOS Operational Amplifiers/' IEEE Trans. Computer-Aided. Design 9(2), pp: 113-125, February 1990.
    • (1990) IEEE Trans. Computer-Aided. Design , vol.9 , Issue.2 , pp. 113-125
    • Koh, H.Y.1    Sequin, C.H.2    Gray, P.R.3
  • 3
    • 0025448791 scopus 로고
    • Analog circuit design optimization based on symbolic simulation and simulated annealing
    • Sept
    • Gielen, G., Wafsharts, H. and Sansen, W., "Analog Circuit Design Optimization Based on Symbolic Simulation and Simulated Annealing." IEEE J. Solid-State Circuits SC-25(3). pp: 707-713. Sept. 1989
    • (1989) IEEE J. Solid-State Circuits SC- , vol.25 , Issue.3 , pp. 707-713
    • Gielen, G.1    Wafsharts, H.2    Sansen, W.3
  • 4
    • 0033702867 scopus 로고    scopus 로고
    • Anaconda: Simulation-based synthesis of analog circuits via stochastic pattern search
    • June
    • Phelps. R.. et al. "Anaconda: Simulation-based synthesis of analog circuits via stochastic pattern search." IEEE Trans. Computer-Aided Design 19(6). pp: 703-717. June 2000.
    • (2000) IEEE Trans. Computer-Aided Design , vol.19 , Issue.6 , pp. 703-717
    • Phelps, R.1
  • 5
    • 0036570097 scopus 로고    scopus 로고
    • Approximate symbolic analysis of hierarchically decomposed analog circuits
    • O. GUERRA. et al. "Approximate Symbolic Analysis of Hierarchically Decomposed Analog Circuits", JNL of Analog Integrated Circuits and Signal Processing. 31, pp: 131-145. 2002
    • (2002) JNL of Analog Integrated Circuits and Signal Processing , vol.31 , pp. 131-145
    • Guerra, O.1
  • 7
    • 0036853822 scopus 로고    scopus 로고
    • Generation of teclinology-independent retargetable analog blocks
    • R. CASTRO-LOPEZ. et al. "Generation of Teclinology-Independent Retargetable Analog Blocks", Analog Integrated Circuits and Signal Processing. 33. pp: 157-170. 2002
    • (2002) Analog Integrated Circuits and Signal Processing , vol.33 , pp. 157-170
    • Castro-Lopez, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.