A Systolic FPGA Architecture of Two-Level Dynamic Programming for Connected Speech Recognition

IEICE Transactions on Information and Systems

Volumn E90-D, Issue 2, 2007, Pages 562-567

  Kim, Yong ^a   Jeong, Hong ^a  

^a Pohang University of Science and Technology (POSTECH)   (South Korea)

Author keywords

FPGA; Hidden Markov model (HMM); Speech recognition; Two level dynamic programming (TLDP)

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MARKOV PROCESSES; RAPID PROTOTYPING; WORD PROCESSING;

HIDDEN MARKOV MODEL (HMM); SPATIAL EFFICIENCY; TWO-LEVEL DYNAMIC PROGRAMMING (TLDP);

SPEECH RECOGNITION;

EID: 33847158266     PISSN: 09168532     EISSN: 17451361     Source Type: Journal    
DOI: 10.1093/ietisy/e90-d.2.562     Document Type: Article

References (15)

1. V. Upadhyaya, S.J. Upadhyaya, and A. Kundu, "A parallel VLSI implementation of Viterbi algorithm for accelerated word recognition," VLSI, 1993. Design Automation of High Performance VLSI Systems, Proceedings. Third Great Lakes Symposium on, pp.37-41, 1993.
2. B.-S. Kim, B. Park, J.-D. Cho, and Y.-H. Chang, "Low power Viterbi search architecture using inverse hidden Markov model," Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on, pp.724-732, 2000.
3. F.L. Vargas, R.D.R. Fagundes, and D.B. Junior, "A FPGA-based Viterbi algorithm implementation for speech recognition systems," Acoustics, Speech, and Signal Processing, 2001. Proceedings. (ICASSP '01). 2001 IEEE International Conference on, vol.2, pp.1217-1220, 2001.
4. J.M. Jou, Y.-H. Shiau, and C.-J. Huang, "An efficient VLSI architecture for HMM-based speech recognition," Electronics, Circuit and Systems, 2001. ICECS 2001. The 8th IEEE International Conference, vol.1, pp.469-472, 2001.
5. B.-G. Park, K.-S. Cho, and J.-D. Cho, "Low power VLSI architecture of Viterbi scorer for HMM-based isolated word recognition," Quality Electronic Design, 2002. Proceedings. International Symposium on, pp.235-239, 2002.
6. S. Yoshizawa, Y. Miyanaga, and N. Wada, "A low-power VLSI design of an HMM based speech recognition system," Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on, vol.2, pp.II-489-II-492, 2002.
7. W. Han, K.-W. Hon, C.-F. Chan, T. Lee, C.-S. Choy, K.-P. Pun, and P.C. Ching, "An HMM-based speech recognition IC," Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, vol.2, pp.II-744-II-747, 2003.
8. F.A. Elmisery, A.H. Khalil, A.E. Salama, and H.F. Hammed, "A FPGA-based HMM for a discrete Arabic speech recognition system," Microelectronics, 2003. ICM 2003. Proceedings of the 15th International Conference on, pp.322-325, 2003.
9. G.C. Caradarilli, A. Malatesta, M. Re, L. Arnone, and S. Bocchio, "Hardware oriented architectures for continuous-speech speaker-independent ASR systems," Signal Processing and Information Technology, 2004. Proceedings of the Fourth IEEE International Symposium on, pp.346-352, Dec. 2004.
10. L.R. Rabiner, "A tutorial on hidden Markov models and selected applications in speech recognition," Proc. IEEE, vol.77, no.2, pp.257-286, 1989.
11. L. Rabiner and B.-H. Juang, Fundamentals of Speech Recognition, pp.321-433, Prentice-Hall, 1993.
12. H. Sakoe, "Two-level DP-matching - A dynamic programming-based pattern matching algorithm for connected word recognition," IEEE Trans. Acoust. Speech Signal Process., vol.27, no.6, pp.588-595, Dec. 1979.
13. S. Nakagawa, "A connected spoken word recognition method by O(n) dynamic programming pattern matching algorithm," IEEE International Conference on ASSP, vol.8, pp.296-299, April 1983.
14. H. Ney, "A comparative study of two search strategies for connected word recognition: Dynamic programming and heuristic search," IEEE Trans. Pattern Anal. Mach. Intell., vol.14, no.5, pp.586-595, May 1992.
15. L.R. Rabiner and R.W. Schafer, Digital Processing of Speech Signals, Prentice-Hall, 1978.