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Volumn 2005, Issue , 2005, Pages 503-506

Differential ring oscillators with multipath delay stages

Author keywords

CMOS VCO; Differential ring oscillator; Jitter and multiphase

Indexed keywords

CMOS INTEGRATED CIRCUITS; JITTER; LOGIC DESIGN; MULTIPATH PROPAGATION;

EID: 33847131935     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2005.1568716     Document Type: Conference Paper
Times cited : (21)

References (7)
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    • J. Kim and M. A. Horowitz, "Adaptive supply serial links with sub- 1V Operation and per-pin clock recovery," IEEE J. Solid State Circuits, vol. 37, no. 11, pp 910-916, Nov. 2002.
    • (2002) IEEE J. Solid State Circuits , vol.37 , Issue.11 , pp. 910-916
    • Kim, J.1    Horowitz, M.A.2
  • 2
    • 0242551728 scopus 로고    scopus 로고
    • Self-biased high-bandwidth low-Jitter 1-to-4096 multiplier clock generator PLL
    • Nov
    • J. Q. Maneatis, J. Kim, I. McClatchie, J. Maxey and M. Shankaradas, "Self-biased high-bandwidth low-Jitter 1-to-4096 multiplier clock generator PLL," IEEE J. Solid State Circuits, vol. 38, no. 11, pp 1795-1803, Nov. 2003.
    • (2003) IEEE J. Solid State Circuits , vol.38 , Issue.11 , pp. 1795-1803
    • Maneatis, J.Q.1    Kim, J.2    McClatchie, I.3    Maxey, J.4    Shankaradas, M.5
  • 3
    • 0027851095 scopus 로고
    • Precise delay generation using coupled oscillators
    • Dec
    • J. Q. Maneatis, and M. Horowitz, "Precise delay generation using coupled oscillators," IEEE J. Solid State Circuits, vol. 28, no. 12, pp 1273-1282, Dec. 1993.
    • (1993) IEEE J. Solid State Circuits , vol.28 , Issue.12 , pp. 1273-1282
    • Maneatis, J.Q.1    Horowitz, M.2
  • 4
    • 0032624146 scopus 로고    scopus 로고
    • A low-noise 900-MHz VCO in 0.6-um CMOS
    • May
    • C. H. Park and B. Kim, "A low-noise 900-MHz VCO in 0.6-um CMOS," IEEE J. Solid State Circuits, vol. 34, no. 5, pp. 586-591, May 1999.
    • (1999) IEEE J. Solid State Circuits , vol.34 , Issue.5 , pp. 586-591
    • Park, C.H.1    Kim, B.2
  • 5
    • 0030291248 scopus 로고    scopus 로고
    • A 320 MHz, 1.5mW @ 1.35 V CMOS PLL for microprocessor clock generation
    • Nov
    • V. von Kaenel, D. Aebischer, C. Piguet, and E. Dijkstra, "A 320 MHz, 1.5mW @ 1.35 V CMOS PLL for microprocessor clock generation," IEEE J. Solid State Circuits, vol. 31, no. 11, pp 1375-1382, Nov. 1996.
    • (1996) IEEE J. Solid State Circuits , vol.31 , Issue.11 , pp. 1375-1382
    • von Kaenel, V.1    Aebischer, D.2    Piguet, C.3    Dijkstra, E.4
  • 6
    • 0242611951 scopus 로고    scopus 로고
    • Optimization of phase-locked loop circuits via geometric programming
    • Sep
    • D. Colleran et al, "Optimization of phase-locked loop circuits via geometric programming," in Proceedings of IEEE Custom Integrated Circuits Conference, Sep. 2003, pp. 377-380.
    • (2003) Proceedings of IEEE Custom Integrated Circuits Conference , pp. 377-380
    • Colleran, D.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.