Minimum emitter charging time for heterojunction bipolar transistors

Conference Proceedings - International Conference on Indium Phosphide and Related Materials

Volumn 2006, Issue , 2006, Pages 325-328

  Machida, N ^a,b   Miyamoto, Y ^a,b   Furuya, K ^a,b  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^b JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SOFTWARE; EMITTER COUPLED LOGIC CIRCUITS; PRODUCT DEVELOPMENT; VOLTAGE CONTROL;

CHARGE-CONTROL ANALYSIS; TRANSMISSION FORMALISM;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 33847129587     PISSN: 10928669     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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9. N. Machida, Y. Miyamoto, and K. Furuya, to be published.