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Volumn 2006, Issue , 2006, Pages
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Performance of FPGA implementation of bit-split architecture for intrusion detection systems
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Author keywords
[No Author keywords available]
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Indexed keywords
ALGORITHMS;
COMPUTER ARCHITECTURE;
INTERFACES (COMPUTER);
PARAMETER ESTIMATION;
SECURITY OF DATA;
THROUGHPUT;
BIT SPLIT ARCHITECTURE;
BITSPLIT ALGORITHMS;
INTRUSION DETECTION SYSTEMS;
MEMORY EFFICIENCY;
FIELD PROGRAMMABLE GATE ARRAYS (FPGA);
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EID: 33847103706
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/IPDPS.2006.1639434 Document Type: Conference Paper |
Times cited : (38)
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References (20)
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