A framework for standard modular simulation in semiconductor wafer fabrication systems

Proceedings - Winter Simulation Conference

Volumn 2005, Issue , 2005, Pages 2162-2171

  Ramírez Hernández, José A ^a   Li, Heshan ^a   Fernandez, Emmanuel ^a   McLean, Charles ^b   Leong, Swee ^b  

^a University of Cincinnati   (United States)

^b NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTER SIMULATION; MATHEMATICAL MODELS; PRODUCTION CONTROL; RESEARCH AND DEVELOPMENT MANAGEMENT; SOCIETIES AND INSTITUTIONS;

FRAMEWORKS; SEMICONDUCTOR FAB MODELS; SEMICONDUCTOR WAFER FABRICATION SYSTEMS;

SILICON WAFERS;

EID: 33846668813     PISSN: 08917736     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/WSC.2005.1574502     Document Type: Conference Paper

References (29)

1. Bhatnagar, S., E. Fernandez-Gaucherand, M. C. Fu, Y. He, and S. I. Marcus. 1999, December. A markov decision process model for capacity expansion and allocation. In Proc. 38th IEEE Conference on Decision and Control, 121-125. Phoenix, AZ.
2. Brooks-Automation 2005. Autosched ap. 〈http://www.autosched. com〉.
3. Campbell, C. E., and J. Ammenheuser. 2000.300 mm factory layout and material handling modeling: phase ii report. Tech transfer document # 99113848beng.
4. Fowler, J. W. 2004. Private communication.
5. Fowler, J. W., M. C. Fu, L. W. Schruben, S. Brown, F. Chance, S. Cunningham, C. Hilton, M. Janakiram, R. Stafford, and J. Hutchby. 1998. Operational modeling & simulation in semiconductor manufacturing. In Proceedings of the 1998 Winter Simulation Conference, 1035-1040.
6. Grewal, N. S., A. C. Bruska, T. M. Wulf, and J. K. Robinson. 1998. Integrating targeted cycle-time reduction into the capital planning process. In Proceedings of the 1998 Winter Simulation Conference, 1005-1010.
7. Kelton, W. D., R. P. Sadowski, and D. T. Sturrock. 2003. Simulation with arena. 3rd ed. USA: McGraw-Hill.
8. Kempf, K. 2005. Intel five-machine six-step mini-fab description. 〈http://www.eas.asu.edu/textasciitilde{}research/intel/papers/fabspec. html〉.
9. Kumar, P. R. 1994. Scheduling semiconductor manufacturing plants. IEEE Control Systems Magazine 39 (11): 33-40.
10. Kumar, S., and P. R. Kumar. 2001. Queueing network models in the design and analysis of semiconductor wafer fabs. IEEE Transactions on Robotics and Automation 17 (5): 548-561.
11. Law, A. M., and W. D. Kelton. 2000. Simulation modeling and analysis. New York: McGraw-Hill Inc.
12. Lee, T., and C. McLean. 2003. A neutral information model for simulation machine shop operations. In Proceedings of the 2003 Winter Simulation Conference, 1296-1304. Pistcataway, New Jersey: Institute of Electrical and Electronic Engineers.
13. Li, H., J. A. Ramírez-Hernández, E. Fernandez, C. R. McLean, and S. Leong. 2005. A framework for standard modular simulation: application to semiconductor wafer fabrication, to be submitted for publication.
14. McLean, C., Y. T. Lee, G. Shao, and F. Riddick. 2005. Shop data model and interface specification, technical report. 〈http://www.sisostds.org/ doclib/doclib.cfm?SISO\_RID\_1005843〉.
15. McLean, C., and S. Leong. 2002. A framework for standard modular simulation. In Proceedings of the 2002 Winter Simulation Conference, 1613-1620. Pistcataway, New Jersey: Institute of Electrical and Electronic Engineers.
16. McLean, C., and G. Shao. 2003. Generic case studies for manufacturing simulation applications. In Proceedings of the 2003 Winter Simulation Conference, 1217-1224. New Jersey: Institute of Electrical and Electronic Engineers.
17. Narahari, Y., and L. M. Khan. 1997. Modeling the effectof hot lots in semiconductor manufacturing systems. IEEE Transactions on Semiconductor Manufacturing 10 (1): 185-188.
18. Object-Managment-Group 2005. Unified modeling language (uml). 〈http://www.uml.org〉.
19. Panwalker, S. S., and W. Iskander. 1977. A survey of scheduling rules. Operation Research 25:45-61.
20. Phillips, T. 1998. Autosched ap by autosimulations. In Proceeding of the 1998 Winter Simulation Conference, 219-222.
21. Plummer, J. D., M. D. Deal, and P. B. Griffin. 2000. Silicon vlsi technology. Englenwood Cliffs, NJ: Prentice-Hall.
22. nd IEEE Conference on Decision and Control, 5926-5931. Maui, HI.
23. Rose, 0.2001. Conwip-like lot release for a wafer fabrication facility with dynamic load changes. In Proceedings of the SMOMS '01 (ASTC '01), 41-46.
24. SEMATECH 1997. Modeling data standards, version 1.0. Technical report, Sematech Inc., Austin, TX.
25. Tsakalis, K. S., J. J. Flores-Godoy, and A. A. Rodriguez. 1997. Hierarchical modeling and control for re-entrant semiconductor fabrication lines: A mini-fab bechmark. In Proceedings of the ETFA'97, 6th IEEE International Conference on Emerging Technology Factory Automation, 514-519. Los Angeles, CA.
26. Uzsoy, R., C. Lee, and L. A. Martin-Vega. 1992. A review of production planning and scheduling models in the semiconductor industry part i: system characteristics, performance evaluation, and production planning. IIE Transactions 24:47-60.
27. Wein, L. M. 1998. Scheduling semiconductor wafer fabrication. IEEE Transactions on Semiconductor Manufacturing 1 (3): 115-130.
28. World-Wide-Web-Consortium 2005. Extensible markup language (xml) 1.0 (third edition). 〈http://www.w3.org/TR/REC-xml.html〉.
29. Yao, X., E. Fernandez-Gaucherand, M. Fu, and S. Marcus. 2004. Optimal preventive maintenance scheduling in semiconductor manufacturing. IEEE Transactions on Semiconductor Manufacturing 17 (23): 345-356.