FPGA-based conformance testing and system prototyping of an MPEG-4 SA-DCT hardware accelerator

Proceedings - 2005 IEEE International Conference on Field Programmable Technology

Volumn 2005, Issue , 2005, Pages 317-318

  Kinane, Andrew ^a   Casey, Alan ^a   Muresan, Valentin ^a   O'Connor, Noel ^a  

^a DUBLIN CITY UNIVERSITY   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

MATHEMATICAL TRANSFORMATIONS; OPTIMIZATION; RAPID PROTOTYPING; REAL TIME SYSTEMS; SYSTEMS ANALYSIS;

FPGA-BASED CONFORMANCE TESTING; REAL TIME CONSTRAINTS; SHAPE ADAPTIVE DISCRETE COSINE TRANSFORM (SA-DCT);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33846624265     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2005.1568579     Document Type: Conference Paper

References (3)

1. T. Sikora and B. Makai, "Shape-Adaptive DCT for Generic Coding of Video," IEEE Trans. Circuits Syst. Video Technol., vol, 5, no. 1, pp. 59-62, Feb. 1995.
2. A. Kinane, V. Muresan, and N. O'Connor, "An Optimal Adder-Based Hardware Architecture for the DCT/SA-DCT,"in Proc. SPIE Video Communications and Image Processing (VCIP), Beijing, China, July 12-15, 2005.
3. Text of ISO/IEC TR 14496-9 Information technology - Coding of audio visual objects - Part 9: Reference hardware description, ISO/IEC Std., Rev. 2, 2005.