A 1.8 GHz CMOS ΔΣ fractional-N synthesizer

European Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 13-16

  De Muer, B ^a   Steyaert, M ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; DIGITAL SYNTHESIZERS; FRACTIONAL SPURS; FRACTIONAL-N FREQUENCY SYNTHESIZERS; FRACTIONAL-N SYNTHESIZER; PHASE DETECTORS; REFERENCE SPUR; SPURIOUS SUPPRESSIONS;

CMOS INTEGRATED CIRCUITS; VARIABLE FREQUENCY OSCILLATORS;

MODULATORS;

EID: 33845637500     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. M. C. T. Riley and T. Kwasniewski, "Delta-sigma modulation in fractional-N frequency synthesis," IEEE Journal of Solid-State Circuits, vol. 28, pp. 553-559, May 1993.
2. J. Yuan and C. Svensson, "New single-clock CMOS latches and flip-flops with improved speed and power savings," IEEE Journal of Solid-State Circuits, vol. 32, pp. 62-69, Jan. 1997.
3. J. Craninckx and M. Steyaert, Low-Phase-Noise Fully Integrated CMOS Frequency Synthesizers. Ph.D. Thesis, K.U. Leuven, 1997.
4. B. De Muer, M. Borremans, N. Itoh, and M. Steyaert, "A 1.8 GHz highly-tunable, low-phase-noise CMOS VCO," in Proceedings Custom Integrated Circuits Conference, (Orlando), pp. 585-588, May 2000.
5. F. Gardner, Phaselock Techniques. J. Wiley & Sons, New York, USA, 1979.
6. B. Goldberg, Digital techniques in frequency synthesis. McGraw-Hill, 1995.
7. T. M. Inc, Matlab user's guide, version 5. Prentice Hall, 1997.
8. W. Rhee, B.-S. Song, and A. Ali, "A 1.1-GHz CMOS Fractional-N Frequency Synthesizer with a 3-b Third-Order-Modulator ," IEEE Journal of Solid-State Circuits, vol. 35, pp. 1453-1460, Oct. 2000.