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Volumn 2006, Issue , 2006, Pages 1118-1121

Wafer thinning solution for wafer-level-capped MEMS devices

Author keywords

[No Author keywords available]

Indexed keywords

ACCELEROMETERS; ELECTRONICS PACKAGING; GRINDING (MACHINING); MICROPROCESSOR CHIPS; TAPES;

EID: 33845595107     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645793     Document Type: Conference Paper
Times cited : (2)

References (8)
  • 1
    • 0002939906 scopus 로고
    • Fabrication technology for an integrated surface micromachined sensor
    • Oct
    • T.A. Core, W.K. Tsang, and S.J. Sherman, "Fabrication Technology for an Integrated Surface Micromachined Sensor," Solid State Technology, Oct 1993, pp. 39-47.
    • (1993) Solid State Technology , pp. 39-47
    • Core, T.A.1    Tsang, W.K.2    Sherman, S.J.3
  • 2
    • 0000214493 scopus 로고    scopus 로고
    • A two-chip accelerometer system for automotive applications
    • F. Shemansky, et. al, "A two-chip accelerometer system for automotive applications," Microsyst. Technol., vol. 1, no. 3, pp. 121-125, 1997
    • (1997) Microsyst. Technol. , vol.1 , Issue.3 , pp. 121-125
    • Shemansky, F.1
  • 5
    • 0142173107 scopus 로고
    • Method for separating circuit dies from a wafer
    • U.S. Patent 5362681, Nov.
    • C.M. Roberts Jr., L.H. Long, and P.A. Ruggerio, "Method for separating circuit dies from a wafer," U.S. Patent 5362681, Nov. 1994
    • (1994)
    • Roberts Jr., C.M.1    Long, L.H.2    Ruggerio, P.A.3
  • 6
    • 0001086601 scopus 로고    scopus 로고
    • New process scheme for wafer thinning and stress-free separation of ultra thin ICs
    • Mesago, Stuttgart
    • C. Landesgerger et al, New Process Scheme for Wafer Thinning and Stress-free Separation of Ultra Thin ICs. Proceedings of Microsystems Technologies 2001, Mesago, Stuttgart, pp. 431-436
    • Proceedings of Microsystems Technologies 2001 , pp. 431-436
    • Landesgerger, C.1
  • 7
    • 33845582690 scopus 로고    scopus 로고
    • Method for manufacturing chip-scale package and manufacturing IC chip
    • U.S. Patent 6338980, January
    • Tetsuo Satoh, "Method for Manufacturing Chip-Scale Package and Manufacturing IC Chip," U.S. Patent 6338980, January 2002
    • (2002)
    • Satoh, T.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.