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Volumn 2006, Issue , 2006, Pages 165-170

Reducing sampling clock jitter to improve SNR measurement of A/D converters in production test

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK JITTERS; CLOCK SIGNALS; QUANTIZATION NOISE; VOLTAGE CONTROLLED CRYSTAL OSCILLATOR (VCXO);

EID: 33845427568     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETS.2006.39     Document Type: Conference Paper
Times cited : (8)

References (13)
  • 1
    • 0003318232 scopus 로고    scopus 로고
    • Beware ATE effects when testing high-speed ADCs
    • June
    • F. Xu, "Beware ATE effects when testing high-speed ADCs," Test and Measurement World, June 1999.
    • (1999) Test and Measurement World
    • Xu, F.1
  • 4
    • 33845397869 scopus 로고    scopus 로고
    • Measureing sub-picosecond jitter in A/D converters for wireless applications
    • Oct.
    • A. Zanchi and I. Papantonopoulos, "Measureing sub-picosecond jitter in A/D converters for wireless applications," Comms Design, Oct. 2004.
    • (2004) Comms Design
    • Zanchi, A.1    Papantonopoulos, I.2
  • 5
    • 33845451207 scopus 로고    scopus 로고
    • Method and system for measuring jitter
    • U.S. Patent 6,640,193
    • T. Kuyel, "Method and System for Measuring Jitter," U.S. Patent 6,640,193.
    • Kuyel, T.1
  • 7
    • 0032305806 scopus 로고    scopus 로고
    • Mixed-signal on-chip timing measurements
    • M. Soma, "Mixed-signal on-chip timing measurements," Integration, the VLSI Journal, no. 26, 1998, pp.151-156.
    • (1998) Integration, the VLSI Journal , Issue.26 , pp. 151-156
    • Soma, M.1
  • 11
    • 0035687180 scopus 로고    scopus 로고
    • A high-resolution jitter measurement technique using ADC sampling
    • S. Cherubal and A. Chatterjee, "A high-resolution jitter measurement technique using ADC sampling," Proc. International Test Conference, 2001, pp. 838-847.
    • (2001) Proc. International Test Conference , pp. 838-847
    • Cherubal, S.1    Chatterjee, A.2
  • 12
    • 84860049723 scopus 로고    scopus 로고
    • Design a low-jitter clock for high-speed data converters
    • Maxim IC application note 800, "Design a low-jitter clock for high-speed data converters," http://www.maxim-ic.com/appnotes.cfm/ appnote_number/800
    • Maxim IC Application Note , vol.800


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.