Reducing sampling clock jitter to improve SNR measurement of A/D converters in production test

Proceedings - Eleventh IEEE European Test Symposium, ETS 2006

Volumn 2006, Issue , 2006, Pages 165-170

  Goyal, Shalabh ^a   Chatterjee, Abhijit ^a   Atia, Mike ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK JITTERS; CLOCK SIGNALS; QUANTIZATION NOISE; VOLTAGE CONTROLLED CRYSTAL OSCILLATOR (VCXO);

ANALOG TO DIGITAL CONVERSION; BANDWIDTH; COMPUTER SIMULATION; PHASE LOCKED LOOPS; SIGNAL TO NOISE RATIO; VARIABLE FREQUENCY OSCILLATORS;

JITTER;

EID: 33845427568     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETS.2006.39     Document Type: Conference Paper

References (13)

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