Massively parallel hardware architecture for genetic algorithms

Proceedings - DSD'2005: 8th Euromicro Conference on Digital System Design - Architectures, Methods and Tools

Volumn 2005, Issue , 2005, Pages 231-234

  Nedjah, Nadia ^a   Mourelle, Luiza De Macedo ^a  

^a STATE UNIVERSITY OF RIO DE JANEIRO   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

FITNESS COMPUTATION PROBLEMS; HARDWARE IMPLEMENTATION; PARALLEL HARDWARE ARCHITECTURE; PROBLEM SPECIFIC KNOWLEDGE;

COMPUTATION THEORY; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; NEURAL NETWORKS; OPTIMIZATION; PROBLEM SOLVING; RESPONSE TIME (COMPUTER SYSTEMS);

GENETIC ALGORITHMS;

EID: 33845295801     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2005.55     Document Type: Conference Paper

References (9)

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5. Michalewics, Z., Genetic algorithms + data structures = evolution programs, Springer-Verlag, Berlin, Second Edition, 1994.
6. Nedjah, N. and Mourelle, L.M., Reconfigurable Hardware Architecture for Compact and Efficient Stochastic Neuron, Artificial Neural Nets Problem Solving Methods, Lecture Notes in Computer Science, vol. 2687, pp. 17-24, 2003.
7. Scott, S.D., Seth, S. and Samal, A., A hardware engine for genetic algorithms, Technical Report, UNL-CSE-97-001, University of Nebraska-Lincoln, July 1997.
8. Turton, B.H. and Arslan, T., A parallel genetic VLSI architecture for combinatorial real-time applications -disc scheduling, In Proc. IEE/IEEE International Conference on genetic Algorithms in Engineering Systems, pp.88-93, 1994.
9. Xilinx, http://www.xilinx.com/, 2004.