Reconfigurable hardware architecture for compact and efficient stochastic neuron

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2687, Issue , 2003, Pages 17-24

  Nedjah, Nadia ^a   De Macedo Mourelle, Luiza ^a  

^a STATE UNIVERSITY OF RIO DE JANEIRO   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL NEURONS; FEED-FORWARD ARTIFICIAL NEURAL NETWORKS; FIELD-PROGRAMMABLE GATE ARRAY; GATE DENSITY; HARDWARE ARCHITECTURE; RE-CONFIGURABLE; RECONFIGURABLE HARDWARES; STOCHASTIC NEURONS; STOCHASTIC PROCESS; STOCHASTIC VALUES; RECONFIGURABLE; STATE OF THE ART;

ARCHITECTURAL DESIGN; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); COMPUTER HARDWARE; HARDWARE; NETWORK ARCHITECTURE; NEURAL NETWORKS; NEURONS; RANDOM PROCESSES; RECONFIGURABLE ARCHITECTURES; STOCHASTIC SYSTEMS;

NEURAL NETWORKS; RECONFIGURABLE HARDWARE;

EID: 26944444392     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44869-1_3     Document Type: Article

References (10)

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