High-voltage LDMOS compact modelling

2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings

Volumn 3, Issue , 2006, Pages 714-719

  Willemsen, M B ^a   Van Langevelde, R ^a   Klaassen, D B M ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

Compact modelling; High voltage; LDMOS

Indexed keywords

CAPACITANCE; CHANNEL CAPACITY; COMPUTER SIMULATION; JUNCTION GATE FIELD EFFECT TRANSISTORS; VOLTAGE MEASUREMENT;

CHANNEL REGION; CIRCUIT SIMULATORS; COMPACT MODELING; INTERNAL NODE;

MOS CAPACITORS;

EID: 33845206588     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. M.B. Willemsen and R. van Langevelde, IEDM2005 Tech. Digest, pp.217-220, 2005.
2. A.C.T. Aarts, R. van der Hout, R. van Langevelde, A.J. Scholten, M.B. Willemsen, and D.B.M. Klaassen, MSM2005, Workshop on Compact Modeling, pp.93-98, 2005.
3. A. Aarts, N. D'Halleweyn and R. van Langevelde, IEEE Trans. on Electron Dev., Vol.ED-52, No.5, pp.999-1007, 2005.
4. www.semiconductors.philips.com/Philips_Models.
5. Y.A. El-Mansy and A.R. Boothroyd, IEEE Trans. on Electron Dev., Vol.ED-24, No.3, pp.254-262, 1977.