-
3
-
-
21144433544
-
Timed automata with urgent transitions
-
R. Barbuti and L. Tesei. Timed automata with urgent transitions. Acta Informatica, 40(5):317-347, 2004.
-
(2004)
Acta Informatica
, vol.40
, Issue.5
, pp. 317-347
-
-
Barbuti, R.1
Tesei, L.2
-
4
-
-
84958037228
-
UPPAAL: A tool suite for automatic verification of real-time systems
-
October
-
J. Bengtsson, K. Larsen, F. Larsson, P. Pettersson, and Y. Wang. UPPAAL: a tool suite for automatic verification of real-time systems. In Proceedings of Workshop on Verification and Control of Hybrid Systems III, LNCS, volume 1066, pages 232-243, October 1995.
-
(1995)
Proceedings of Workshop on Verification and Control of Hybrid Systems III, LNCS
, vol.1066
, pp. 232-243
-
-
Bengtsson, J.1
Larsen, K.2
Larsson, F.3
Pettersson, P.4
Wang, Y.5
-
5
-
-
84949238101
-
Modeling urgency in timed systems
-
Springer Verlag
-
S. Bornot, J. Sifakis, and S. Tripakis. Modeling urgency in timed systems. In Compositionality, LNCS, volume 1536. Springer Verlag, 1997.
-
(1997)
Compositionality, LNCS
, vol.1536
-
-
Bornot, S.1
Sifakis, J.2
Tripakis, S.3
-
6
-
-
33845192738
-
Automatic verification of a lip synchronisation algorithm using UPPAAL - Extended version
-
May
-
H. Bowman, G. Faconti, J-P. Katoen, D. Latella, and M. Massink. Automatic verification of a lip synchronisation algorithm using UPPAAL -extended version-. Third Intematinoal Workshop on Formal Methods for Industrial Critical Systems, pages 97-124, May 1998.
-
(1998)
Third Intematinoal Workshop on Formal Methods for Industrial Critical Systems
, pp. 97-124
-
-
Bowman, H.1
Faconti, G.2
Katoen, J.-P.3
Latella, D.4
Massink, M.5
-
7
-
-
0038565213
-
IF: An intermediate representation and validation environment for time asynchronous systems
-
M. Bozga, J. Cl. Fernandez, L. Ghirvu, S. Graf, J.P Krimm, and L. Mounier. IF: An intermediate representation and validation environment for time asynchronous systems. In Proceedings of the Formal Methods Conference (FM), 1999.
-
(1999)
Proceedings of the Formal Methods Conference (FM)
-
-
Bozga, M.1
Fernandez, J.Cl.2
Ghirvu, L.3
Graf, S.4
Krimm, J.P.5
Mounier, L.6
-
8
-
-
85037030721
-
Design and sythesis of synchronization skeletons using branching time temporal logic
-
Proceedings of the Logics of Programs Workshop, Springer Verlag
-
E.M. Clarke and E.A. Emerson. Design and sythesis of synchronization skeletons using branching time temporal logic. In Proceedings of the Logics of Programs Workshop, volume 131 of LNCS, pages 52-71. Springer Verlag, 1981.
-
(1981)
LNCS
, vol.131
, pp. 52-71
-
-
Clarke, E.M.1
Emerson, E.A.2
-
9
-
-
84944099472
-
Timing assumptions and verification of finite-state concurrent systems
-
Proceedings of Workshop on Automatic Verification Methods for Finite State Systems, Springer-Verlag
-
David L. Dill. Timing assumptions and verification of finite-state concurrent systems. In Proceedings of Workshop on Automatic Verification Methods for Finite State Systems, volume 407 of LNCS, pages 197-212. Springer-Verlag, 1989.
-
(1989)
LNCS
, vol.407
, pp. 197-212
-
-
Dill, D.L.1
-
11
-
-
0347566217
-
Timed I/O automata: A mathematical framework for modeling and analyzing real-time systems
-
IEEE CS Press, December
-
D. K. Kaynar, N. Lynch, R. Segala, and F. Vaandrager. Timed I/O automata: A mathematical framework for modeling and analyzing real-time systems. In Proceedings of the 24th IEEE International Real-Time Systems Symposium (RTSS), pages 166-177. IEEE CS Press, December 2003.
-
(2003)
Proceedings of the 24th IEEE International Real-time Systems Symposium (RTSS)
, pp. 166-177
-
-
Kaynar, D.K.1
Lynch, N.2
Segala, R.3
Vaandrager, F.4
-
12
-
-
33646166591
-
Model checking prioritized timed automata
-
Springer Verlag, October
-
S.-W. Lin, P.-A. Hsiung, C.-H. Huang, and Y.-R. Chen. Model checking prioritized timed automata. In Proceedings of the 3rd International Symposium on Automated Technology for Verification and Analysis (ATVA, Taipei, Taiwan), LNCS, volume 3707. Springer Verlag, October 2005.
-
(2005)
Proceedings of the 3rd International Symposium on Automated Technology for Verification and Analysis (ATVA, Taipei, Taiwan), LNCS
, vol.3707
-
-
Lin, S.-W.1
Hsiung, P.-A.2
Huang, C.-H.3
Chen, Y.-R.4
-
13
-
-
0026838260
-
Computational model for distributed multimedia application based on a synchronous programming language
-
J-B Stefani, L. Hazard, and F.Horn. Computational model for distributed multimedia application based on a synchronous programming language. Computer Communications (Special Issue on FDTs), 15(2), 1992.
-
(1992)
Computer Communications (Special Issue on FDTs)
, vol.15
, Issue.2
-
-
Stefani, J.-B.1
Hazard, L.2
Horn, F.3
-
14
-
-
35048819139
-
RED: Model-checker for timed automata with clock-restriction diagram
-
August Technical Report 2001-014, ISSN 1404-3203, Department of Information Technology, Uppsala University
-
F. Wang, RED: Model-checker for timed automata with clock-restriction diagram. In Proceedings of the Workshop on Real-Time Tools, August 2001. Technical Report 2001-014, ISSN 1404-3203, Department of Information Technology, Uppsala University.
-
(2001)
Proceedings of the Workshop on Real-time Tools
-
-
Wang, F.1
-
15
-
-
0036158371
-
Efficient and user-friendly verification
-
January
-
F. Wang and P.-A. Hsiung. Efficient and user-friendly verification. IEEE Transactions on Computers, 51(1):61-83, January 2002.
-
(2002)
IEEE Transactions on Computers
, vol.51
, Issue.1
, pp. 61-83
-
-
Wang, F.1
Hsiung, P.-A.2
|