From 120 to 32 nm CMOS technology: development of OPC and RET to rescue optical lithography

Comptes Rendus Physique

Volumn 7, Issue 8, 2006, Pages 887-895

  Trouiller, Yorick ^a  

^a CEA LETI   (France)

Author keywords

OPC; Optical lithography; RET

Indexed keywords

EID: 33751506158     PISSN: 16310705     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.crhy.2006.10.001     Document Type: Short Survey

References (6)

1. N. Cobb, Fast optical and process proximity correction algorithms for integrated circuit manufacturing, PhD thesis 1998, University of California, Berkeley
2. Painter B., et al. Classical control theory applied to OPC correction segment convergence. Proc. SPIE 5377 (2004) 1198-1206
3. Borjon A., et al. High accuracy 65 nm OPC verification: Full process window model vs. critical failure ORC. Proc. SPIE 5754 (2005) 1190-1201
4. Adams D.S., et al. Fast inverse lithography technology. Proc. SPIE 6154 (2006) 61541J
5. Tritchkov A., et al. Lithography enabling for the 65 nm node gate layer patterning with alternated PSM. Proc. SPIE 5754 (2005) 215-225
6. Liebmann L., et al. Reducing DfM to practice: the lithography manufacturability assessor. Proc. SPIE 6156 (2006) 61560K