The quest of porous ELK materials for high performance logic technologies

Microelectronic Engineering

Volumn 83, Issue 11-12, 2006, Pages 2055-2058

  Hsia, Chin C ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Effective Modulus (B); Etch Stop Layer; Extreme low k; k Process; Trench First Hard Mask Via First

Indexed keywords

DIELECTRIC MATERIALS; ELECTRON BEAMS; ELECTRONICS PACKAGING; FINITE ELEMENT METHOD; FORMAL LOGIC; PERMITTIVITY;

EFFECTIVE MODULUS (B); ETCH STOP LAYERS; EXTREME LOW K; K PROCESS; TRENCH FIRST HARD MASK VIA FIRST;

POROUS MATERIALS;

EID: 33751345851     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2006.09.007     Document Type: Article

References (4)

1. M.S. Liang, in: Challenges in Cu/Low-K Integration, IEDMS, 2004.
2. M.D. Lei et al., in: In-line Semi-electrical Process Diagnosis Methodology for Integrated Process Window Optimization of 65 nm and below Technology Nodes, SPIE, 2006.
3. T.C. Huang et al., in: Wire Bonding Failure Mechanisms and Simulations of Cu Low-K IMD Chip Packaging, AMC, 2002.
4. Hau-Riege S.P., and Thompson C.V. J. Mater. Res. 15 8 (2000) 1797-1802