Gate disturb reduction in a silicon nanocrystal flash EEPROM by means of natural threshold voltage reduction

21st IEEE Non-Volatile Semiconductor Memory Workshop 2006, NVSMW 2006

Volumn 2006, Issue , 2006, Pages 56-57

  Swift, Craig T ^a   Hoefler, Alex ^a   Kirichenko, Taras ^a   Muralidhar, Ramachandran ^a   Prinz, Erwin ^a   Rao, Rajesh ^a   Rinkenberger, Glenn ^a   Sadd, Michael ^a   Steimle, Robert ^a  

^a FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33751051510     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2006.1629492     Document Type: Conference Paper

References (6)

1. R. Muralidhar, et al., IEDM, Dec. 2003, p. 601.
2. R. Steimle, et al., IEEE Conf. on Nanotechnology, Aug. 2004, p. 290.
3. C. Swift, et al., IEDM, Dec. 2002, p. 927.
4. M. Sadd, et al., NVSMW, 2001, p. 82.
5. P. Stolk, et al., TED, Vol. 45, No. 9, Sept. 1998, p. 1960.
6. D. Burnett, et al., IEDM, Dec. 2002, p. 529.