The nonidealities of multibit continuous-time sigma delta modulators

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2003, Pages 790-793

  Samid, Lourans ^a   Manoli, Yiannos ^a  

^a UNIVERSITY OF FREIBURG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK-JITTER; CONTINUOUS TIME; LOW-PASS; MULTI-BITS; MULTI-HIT; NON-IDEALITIES; OVER SAMPLING RATIO; POWER DISSIPATION; SIGMA DELTA MODULATOR; SIMULATION RESULT; THIRD ORDER; CONTINUOUS-TIME; CONTINUOUS-TIME SIGMA-DELTA MODULATORS;

CONTINUOUS TIME SYSTEMS; DELTA MODULATION; JITTER; DELTA SIGMA MODULATION; RADIO RECEIVERS;

MODULATORS;

EID: 33751025067     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2003.1301905     Document Type: Conference Paper

References (6)

1. O. Shoaei, Continuous-Tim Delta-Sigma A/D Converters for High Speed Applications, Ph.D. thesis, Carleton University, Ottawa, Canada, 1995.
2. J.A. Cherry et. al, "Excess loop delay in continuoustime delta-sigma moduliitors," IEEE Transactions on Circuits and Sysrems -11, pp. Vo1.46,N0.4,37&389, April 1999.
3. A. Marques et. al, "Optimal Parameter for Sigma-Delta Modulator Topologies," IEEE Transactions on Circuits and systems -11, pp. Vo1.45,N0.9,1232-12l, September 1998.
4. G.C. Temes J. C. Candy, Oversampling Delta -Sigma Data Conveter, IEEE, 1992.
5. W.M.C. Sansen K.R. Laker, Design of Analog Integrated Circuits and System, McGraw-Hill, 1994.
6. F Medeiro et. al, Top-Down design of high performnce Sigma-Delta Modulators, Kluwer, 1999