A practical approach for monitoring analog circuits

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn 2006, Issue , 2006, Pages 330-335

  Zaki, Mohamed H ^a   Tahar, Sofiène ^a   Bois, Guy ^b  

^a Dept of Electrical and Computer Engineering   (Canada)

^b ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

Verification

Indexed keywords

AUTOMATA THEORY; DIGITAL CONTROL SYSTEMS; DIODES; ELECTRIC NETWORK ANALYSIS; LOGIC DESIGN; OSCILLATIONS; TUNNEL DIODE OSCILLATORS;

DIGITAL DESIGN; MIXED SIGNAL SYSTEMS; OSCILLATION PROPERTIES; VERIFICATION;

ANALOG COMPUTERS;

EID: 33750909111     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1127908.1127984     Document Type: Conference Paper

References (18)

1. R. Alur, C. Courcoubetis, D. L. Dill. Model-checking in dense realtime. Journal of Information and Computation, 104(1):2-34, 1993.
2. I. Beer, et. al. The Temporal Logic Sugar. In Computer Aided Verification, LNCS 2102, Springer, 2001, pp. 363-367
3. T. Dang, A. Donze, O.Maler. Verification of Analog and Mixed-signal Circuits using hybrid system techniques. In Formal Methods in Computer-Aided Design, LNCS 3312, Springer: 14-17, 2004.
4. G. Frehse, B. Krogh, R. Rutenbar, O. Maler Time Domain Verification of Oscillator Circuit Properties, Workshop on Formal Verification of Analog Circuits. April 9th, 2005, Edinburgh, UK.
5. M. Geilen. An Improved On-The-Fly Tableau Construction for a Real-Time Temporal Logic. In Computer Aided Verification, LNCS 2725, Springer, 2003, pp. 394-406.
6. M.C.W. Geilen. Formal Techniques for Verification of Complex Real-time Systems, Ph.D. Thesis, Eindhoven University of Technology, 2002
7. M. R. Greenstreet, I. Mitchell. Reachability Analysis Using Polygonal Projections. In Hybrid Systems: Computation and Control, LNCS 1569, Springer. 1999, pp.103-116.
8. S.Gupta, B.H. Krogh, R.A. Rutenbar. Towards Formal Verification of Analog Designs, IEEE/ACM International Conference on Computer Aided Design. 2004, pp.210 - 217.
9. W. Hartong, R. Klausen, L. Hedrich. Formal Verification for Nonlinear Analog Systems: Approaches to Model and Equivalence Checking, In Advanced Formal Verification, Kluwer, 2004, pp. 205-245.
10. L. Hedrich and E. Barke. A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances. IEEE/ ACM Design, Automation and Test in Europe, 1998, pp. 649-654.
11. A. Lemke, L. Hedrich, and E. Barke, Analog Circuit Sizing Based on Formal Methods Using Affine Arithmetic. IEEE/ ACM International Conference on Computer Aided Design, 2002, pp. 486-489.
12. R. J. Lohner, Enclosing the solutions of ordinary initial and boundary value problems, in Computer Arithmetic: Scientific Computation and Programming Language, Wiley-Teubner Series in Computer Science, Stuttgart, 1987, pp.255-286
13. R.P. Kurshan and K.L. McMillan. Analysis of digital circuits through symbolic reduction. IEEE Transaction on Computer-Aided Design 10:pp.1350-1371, 1991.
14. M. Maidl. The Common Fragment of CTL and LTL. Proc. Annual Symposium on Foundations of Computer Science, IEEE Computer Society, 2000, pp.643-652.
15. O. Maler, D. Nickovic, Amir Pnueli. Real Time Temporal Logic: Past, Present, Future. In International Conference on Formal Modelling and Analysis of Timed Systems, LNCS 3829, Springer, 2005, pp.2-16
16. O. Maler, D. Nickovic. Monitoring Temporal Properties of Continuous Signals. In International Conference on Formal Modelling and Analysis of Timed System, LNCS 3253, Springer, 2004, pp.152-166
17. R. E. Moore, Methods and Applications of Interval Analysis, Society for Industrial and Applied Mathematics, 1979.
18. L. Tan, J. Kim, I. Lee. Testing and Monitoring Model-based Generated Program. In Proc. Run-time Verification, Electronic Notes in Theoretical Computer Science, 89(2), 2003