DBNS addition using cellular neural networks

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 3914-3917

  Ibrahim, Y ^a   Miller, W C ^a   Jullien, G A ^b   Dimitrov, V S ^b  

^a UNIVERSITY OF WINDSOR   (Canada)

^b UNIVERSITY OF CALGARY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; DIGITAL LOGIC; DOUBLE BASE NUMBER SYSTEM; LOW NOISE; MIXED-SIGNAL CIRCUITS; NON-ZERO DIGITS; NOVEL ARCHITECTURE;

ADDERS; ANALOG CIRCUITS; CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS;

CELLULAR NEURAL NETWORKS;

EID: 33750585668     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465486     Document Type: Conference Paper

References (13)

1. A. A. Avizienis, A Study of Redundant Number Representations for Parallel Digital Computers, Ph.D. Thesis, University of Illinois, 1960.
2. V. S. Dimitrov, S. Sadeghi-Emamchaie, G. A. Jullien and W. C. Miller, "A near canonic double-base number system with applications in DSP," SPIE Conference on Signal Processing Algorithms, vol. 2846, pp. 14-25, 1996.
3. L. O. Chua and T. Roska, Cellular Neural Networks and Visual Computing: Foundations and Applications, Cambridge University Press, 2002, ISBN 0 521 65247 2.
4. S. Sadeghi-Emamchaie, G. A. Jullien, V. S. Dimitrov and W. C. Miller, "Digital arithmetic using cellular neural networks," Journal of Circuits, Systems and Computers, No. 8, vol. 6, pp. 515-535, Dec. 1998.
5. L. O. Chua, L. Yang, "Cellular neural networks," IEEE Trans. Circuits Syst., 35, 10, pp. 1257-1272, 1988.
6. L. O. Chua, and L. Yang, "Cellular neural networks: applications," IEEE Trans. Circuits Syst., 35, 10, pp. 1273-1290, 1988.
7. P. Kornerup, "Computer arithmetic: exploiting redundancy in number representations," ASAP95, Strasbourg.
8. V. S. Dimitrov and G. A. Jullien, "Loading the bases: a new number representation with applications," invited article in IEEE Circuits and Systems Magazine, 2nd Quarter, pp. 6-23, 2003.
9. M. Ercegovac and T. Lang, Digital Arithmetic, Morgan Kaufmann Publishers, 2003, ISBN 1 558 60798 6.
10. P. Kinget, and M. Steyaert, Analog VLSI Integration of Massive Parallel Processing Systems, Kluwer Academic Publishers, 1997.
11. T. Roska and L. O. Chua, "The CNN universal machine: an analogic array computer," IEEE Trans. CAS. II, 40, pp. 163-173, Mar. 1993.
12. S. Espejo, R. Domínguez-Castro, G. Liñán, and á. Rodríguez-Vázquez, "A 64x64 CNN universal chip with analog and digital I/O," in Proc. 5th IEEE Int. Conf. Electronics, Circuits and Systems, (ICECS'98), Lisbon, Portugal, 1998, pp. 203-206.
13. H. Kim, T. Roska, H. Son, and I. Petras, "Analog addition/subtraction on the CNN-UM chip with short-time superimposition of input signals," IEEE Trans. CAS. I, 50, 3, pp. 429-432, Mar. 2003.