Optimal drive signals design and implementation in CPLD for medium voltage three-level inverter equipped with IGCTS

Zhongguo Dianji Gongcheng Xuebao/Proceedings of the Chinese Society of Electrical Engineering

Volumn 26, Issue 17, 2006, Pages 51-56

  Cui, Zhi Liang ^a   Zhao, Zheng Ming ^a   Yuan, Li Qiang ^a   Yi, Rong ^a  

^a State Key Lab of Control and Simulation of Power Systems and Generation Equipments   (China)

Author keywords

Complex programmable logic device; Dead time; Integrated gate commutated thyristor; Minimum pulse width; Power electronics; Three level inverter

Indexed keywords

ELECTRIC POTENTIAL; LOGIC DEVICES; POWER ELECTRONICS; PULSE WIDTH MODULATION; RELIABILITY; THYRISTORS;

COMPLEX PROGRAMMABLE LOGIC DEVICE (CPLD); DEAD TIME; DRIVE SIGNALS OPTIMAL METHOD; INTEGRATED GATE COMMUTATED THYRISTOR (IGCT); MINIMUM PULSE WIDTH; THREE LEVEL INVERTER;

ELECTRIC INVERTERS;

EID: 33750579050     PISSN: 02588013     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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