Loading allocation algorithm with machine capability restrictions for wafer fabrication factories

Kung Yeh Kung Chieng Hsueh K'an/Journal of the Chinese Institute of Industrial Engineers

Volumn 18, Issue 4, 2001, Pages 82-96

  Chung, Shu Hsing ^a   Huang, Hung Wen ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Capacity requirement planning; Loading allocation; Wafer fabrication

Indexed keywords

EID: 33750554120     PISSN: 10170669     EISSN: None     Source Type: Journal    
DOI: 10.1080/10170660109509496     Document Type: Article

References (9)

1. Atherton, L. F. and R. W. Atherton, Wafer Fabrication: Factory Performance and Analysis, Kluwer Academic Publishers (1995).
2. Blackstone, J. H, Capacity Management, South-Western Publishing CO. (1989).
3. Chung, S. H. and H. W. Huang, "The block-based cycle time estimation algorithm for wafer fabrication factories," International Journal of Industrial Engineering, accepted in Dec (1998).
4. Giegling, S., T. Haymon, W. A. Verdini and J. Konopka, "Implement of overall equipment effectiveness (OEE) system at a semiconductor manufactor," IEEE/CPMT International Electronic Manufacturing Technology Symposium, 93-98 (1997).
5. Huang, H. W. and S. H. Chung, "The design of constraint-oriented target planning system for wafer fabrication factories," Proceedings of Joint Conference of The International Conference on Automation Technology and 1998 International Conference of Production Research (Asia Meeting), A3-1 (1998).
6. Konopka, J. M., "Capacity utilization bottleneck efficiency system - CUBES," IEEE Transaction on Component, Packaging, and Manufacturing Technology-Part A, 18(3) (1995).
7. Leachman R. C., "Closed-loop measurement of equipment efficiency and equipment capacity," IEEE Transactions on Semiconductor Manufacturing, 10(1) (1997).
8. Murphy, R., P. Saxenz and W. Levinson, "Use OEE; don't let OEE use you," Semiconductor International, Semptmber(1996).